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Paper Abstract and Keywords
Presentation 2015-03-02 10:35
[Invited Talk] Integration Technology of 3D FPGA with Performance Scalability and Function Flexibility
Kenichi Takeda, Mayu Aoki (Hitachi) SDM2014-163
Abstract (in Japanese) (See Japanese page) 
(in English) Three-layer stacked wafer with CMOS devices was demonstrated by using hybrid wafer bonding and via-last through silicon via (TSV) processes. We confirmed that copper/polymer hybrid wafer bonding provides both good bump bonding and voidless underfilling in Face-to-face (F2F) and Back-to-face (B2F). By using backside-via last TSV processes, good electrical connection between TSV and copper/low-k interconnect was successfully obtained without low-k degradation. The highest level transmission performance of 15 Tbps/W was achieved by actualizing low-capacitance TSV (around 40 fF). Additionally, Keep-out-zone (KOZ) was estimated lower than 2 μm according to the ring oscillator measurements. This small KOZ is mainly attributed to low Si stress (~100 MPa at 2 μm distance from TSV edge).
Keyword (in Japanese) (See Japanese page) 
(in English) TSV / Wafer bonding / Via-last / Copper bonding / KOZ / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 469, SDM2014-163, pp. 7-11, March 2015.
Paper # SDM2014-163 
Date of Issue 2015-02-23 (SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2014-163

Conference Information
Committee SDM  
Conference Date 2015-03-02 - 2015-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg 
Topics (in Japanese) (See Japanese page) 
Topics (in English) http://www.ieice.org/jpn/about/syozai.html 
Paper Information
Registration To SDM 
Conference Code 2015-03-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Integration Technology of 3D FPGA with Performance Scalability and Function Flexibility 
Sub Title (in English)  
Keyword(1) TSV  
Keyword(2) Wafer bonding  
Keyword(3) Via-last  
Keyword(4) Copper bonding  
Keyword(5) KOZ  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Kenichi Takeda  
1st Author's Affiliation Hitachi, Ltd. (Hitachi)
2nd Author's Name Mayu Aoki  
2nd Author's Affiliation Hitachi, Ltd. (Hitachi)
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Speaker Author-1 
Date Time 2015-03-02 10:35:00 
Presentation Time 30 minutes 
Registration for SDM 
Paper # SDM2014-163 
Volume (vol) vol.114 
Number (no) no.469 
Page pp.7-11 
#Pages 5 
Date of Issue 2015-02-23 (SDM) 

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