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| Presentation | 2015-03-03 09:40 Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.)  VLD2014-163 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We analyze the efficiency of the design methodology by using circuit simulations. The design methodology which considers the correlation between process variations and BTI (Bias Temperature Instability)-induced degradations reduces timing margins of circuits without threatening their reliability. Because the reliability issues become significant problems in the heavily scaled process, circuit designers should consider them. The reliable design methodology for high performance circuits is required. There is the correlation between process variations and BTI-induced degradations. The degradation rates of MOSFETs which have low initial threshold voltages are lower than the other variation conditions. We propose the design methodology which considering the correlation and analyze its efficiency for circuit designs. We confirm the timing margins are reduced by 10% with our methodology. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | BTI / process variation / reliability / degradation prediction / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 476, VLD2014-163, pp. 61-66, March 2015. | |
| Paper # | VLD2014-163 | |
| Date of Issue | 2015-02-23 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-163 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2015-03-02 - 2015-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2015-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI |
| Sub Title (in English) | |
| Keyword(1) | BTI |
| Keyword(2) | process variation |
| Keyword(3) | reliability |
| Keyword(4) | degradation prediction |
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| Keyword(8) | |
| 1st Author's Name | Michitarou Yabuuchi |
| 1st Author's Affiliation | Kyoto Institute of Technology (Kyoto Inst. of Tech.) |
| 2nd Author's Name | Kazutoshi Kobayashi |
| 2nd Author's Affiliation | Kyoto Institute of Technology (Kyoto Inst. of Tech.) |
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| Speaker | Author-1 |
| Date Time | 2015-03-03 09:40:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2014-163 |
| Volume (vol) | vol.114 |
| Number (no) | no.476 |
| Page | pp.61-66 |
| #Pages | 6 |
| Date of Issue | 2015-02-23 (VLD) |
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