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Paper Abstract and Keywords
Presentation 2015-03-04 13:00
An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework
Satoshi Ohtsuki, Atsushi Takahashi (Tokyo Tech) VLD2014-181
Abstract (in Japanese) (See Japanese page) 
(in English) In the current typical of integrated circuits, the performance is determined by the maximum delay between flip-flops. Therfore, the reduction of the maximum delay has been pursured, however, it approaches the limit. In the circuits with the error detection/correction system, the performance is bounded by the clock period and delay error rate.
In this paper, we discuss a relation between clock period and delay error rate on a circuit which has high error rate. We evaluate the performance of variable-latency circuit of a multiplier with error-detection/correction system on FPGA.
Keyword (in Japanese) (See Japanese page) 
(in English) error-detection/correction system / clock period / delay error rate / multiplier / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 476, VLD2014-181, pp. 159-164, March 2015.
Paper # VLD2014-181 
Date of Issue 2015-02-23 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-181

Conference Information
Committee VLD  
Conference Date 2015-03-02 - 2015-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2015-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework 
Sub Title (in English)  
Keyword(1) error-detection/correction system  
Keyword(2) clock period  
Keyword(3) delay error rate  
Keyword(4) multiplier  
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1st Author's Name Satoshi Ohtsuki  
1st Author's Affiliation Tokyo Insutitued of technology (Tokyo Tech)
2nd Author's Name Atsushi Takahashi  
2nd Author's Affiliation Tokyo Insutitued of technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2015-03-04 13:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2014-181 
Volume (vol) vol.114 
Number (no) no.476 
Page pp.159-164 
#Pages 6 
Date of Issue 2015-02-23 (VLD) 

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