| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2015-03-04 09:15 On PLL Layouts Evaluation based on Transistor-array Style Yuki Miura, Atsushi Nanri, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu)  VLD2014-175 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The transistor array(TA)-style is a layout methodology where an analog layout is configured on the pattern such that unit-transistors of the same size form an array. It contributes to an easy implementation of design automation, and it also serves a design to mitigate the process variability in 90$nm$ beyond. In this work, utilizing a phase locked loop(PLL) circuit as a motif, we verify the relationship between the fine processes and TA-style. We generate the layouts of the PLL based on the TA-style on 0.6$mu m$, 180$nm$, 65$nm$ in three processes, and compare them with respect to the area and the post-layout simulation results of the control voltage of the VCO. Besides, we also generate a custom layout in 0.6$mu m$ process, and fabricate the chip. We report the compare resut with the TA-style one. |
|
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Analog layout / Phase locked loop / Transistor array / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 476, VLD2014-175, pp. 123-128, March 2015. | |
| Paper # | VLD2014-175 | |
| Date of Issue | 2015-02-23 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-175 |
|
| Conference Information | |
| Committee | VLD |
| Conference Date | 2015-03-02 - 2015-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2015-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On PLL Layouts Evaluation based on Transistor-array Style |
| Sub Title (in English) | |
| Keyword(1) | Analog layout |
| Keyword(2) | Phase locked loop |
| Keyword(3) | Transistor array |
| Keyword(4) | |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yuki Miura |
| 1st Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
| 2nd Author's Name | Atsushi Nanri |
| 2nd Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
| 3rd Author's Name | Qing Dong |
| 3rd Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
| 4th Author's Name | Shigetoshi Nakatake |
| 4th Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2015-03-04 09:15:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2014-175 |
| Volume (vol) | vol.114 |
| Number (no) | no.476 |
| Page | pp.123-128 |
| #Pages | 6 |
| Date of Issue | 2015-02-23 (VLD) |
[Return to Top Page]