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| Presentation | 2015-03-07 08:55 Improvements and evaluation of bias circuit control for CMOS analog circuit Ryohei Hori (Ritsumeikan Univ.), Toshio Kumamoto (OSU), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.)  CPSY2014-175 DC2014-101 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The power control using Noff (Normally-off) scheme for realization low power sensor node device is gathering a lot of attention. It is the technology that reduces power consumptions by cutting power-supplies for unused hardware even if application is running. To realize Noff scheme for analog circuits, the controlling active state and non-active state in analog circuit devices by bias circuits is proposed. A bias circuit is a part of the analog circuits which generates intermediate voltages for analog operation. In this paper, Improvement of bias circuit for Noff scheme is proposed. The structure of novel bias circuit reduces power consumption while active state. With SPICE simulation, the total current consumption in settling time and the average current consumption in active time are reduced by about 57.8% and 68.0% compared with existing bias circuit. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Normally-off / Bias Circuit / CMOS analog circuit / Settling time / Low Power / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 506, CPSY2014-175, pp. 77-82, March 2015. | |
| Paper # | CPSY2014-175 | |
| Date of Issue | 2015-02-27 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2014-175 DC2014-101 |
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| Conference Information | |
| Committee | CPSY IPSJ-EMB IPSJ-SLDM DC |
| Conference Date | 2015-03-06 - 2015-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2015-03-CPSY-EMB-SLDM-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Improvements and evaluation of bias circuit control for CMOS analog circuit |
| Sub Title (in English) | |
| Keyword(1) | Normally-off |
| Keyword(2) | Bias Circuit |
| Keyword(3) | CMOS analog circuit |
| Keyword(4) | Settling time |
| Keyword(5) | Low Power |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ryohei Hori |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Toshio Kumamoto |
| 2nd Author's Affiliation | Osaka Sangyo University (OSU) |
| 3rd Author's Name | Masayoshi Shirahata |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name | Takeshi Fujino |
| 4th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-03-07 08:55:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | CPSY2014-175, DC2014-101 |
| Volume (vol) | vol.114 |
| Number (no) | no.506(CPSY), no.507(DC) |
| Page | pp.77-82 |
| #Pages | 6 |
| Date of Issue | 2015-02-27 (CPSY, DC) |
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