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| Presentation | 2015-04-17 14:15 Parallel Processor Architecture based on Small World Connection Hideki Mori (Meiji Univ.), Minoru Uehara, Katsuyoshi Matsumoto (Toyo Univ.)  CPSY2015-10 DC2015-10 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The technology of circuit refinement has achieved a tremendous large-scale integration, so huge VLSI systems have emerged. However, in the huge VLSI systems, various problems, such as latency, power dissipation bottlenecks and clock synchronization of the entire system, must be solved in order to realize a dependable and safe system. Small World Network allows communication between arbitrary nodes where hopping over a small number of nodes is possible in a network with a huge number of nodes. In this paper, our aim is to introduce a parallel architecture with short path communication, featuring a random connection in Small World Network. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | parallel system / average path length / average clustering coefficient / small world network / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 7, CPSY2015-10, pp. 53-58, April 2015. | |
| Paper # | CPSY2015-10 | |
| Date of Issue | 2015-04-10 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2015-10 DC2015-10 |
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| Conference Information | |
| Committee | DC CPSY |
| Conference Date | 2015-04-17 - 2015-04-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2015-04-DC-CPSY |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Parallel Processor Architecture based on Small World Connection |
| Sub Title (in English) | |
| Keyword(1) | parallel system |
| Keyword(2) | average path length |
| Keyword(3) | average clustering coefficient |
| Keyword(4) | small world network |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Hideki Mori |
| 1st Author's Affiliation | Meiji University (Meiji Univ.) |
| 2nd Author's Name | Minoru Uehara |
| 2nd Author's Affiliation | Toyo University (Toyo Univ.) |
| 3rd Author's Name | Katsuyoshi Matsumoto |
| 3rd Author's Affiliation | Toyo University (Toyo Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-04-17 14:15:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | CPSY2015-10, DC2015-10 |
| Volume (vol) | vol.115 |
| Number (no) | no.7(CPSY), no.8(DC) |
| Page | pp.53-58 |
| #Pages | 6 |
| Date of Issue | 2015-04-10 (CPSY, DC) |
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