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Paper Abstract and Keywords
Presentation 2015-05-14 15:25
AES Encryption Circuit against Clock Glitch based Fault Analysis
Daisuke Hirano, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ) VLD2015-7
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, fault analysis has attracted a lot of attentions as a new kind of side channel attack methods,in which malicious faults are generally injected by attackers through clock glitch generation, voltage change, or laser manipulation during the execution of a crypto circuit.
As existing countermeasures against fault analysis, area-redundant and time-redundant methods have been proposed. However they will cause large area overhead or time overhead. Therefore, in this paper, we proposed an AES circuit design that can detect timing faults caused by malicious clock glitches.
Experimental results show that the proposed method can detect 100% timing faults at only 4.9% post-layout area overhead.
Keyword (in Japanese) (See Japanese page) 
(in English) advanced encryption standard / side-channel attacks / fault analysis / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 21, VLD2015-7, pp. 51-55, May 2015.
Paper # VLD2015-7 
Date of Issue 2015-05-07 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2015-7

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2015-05-14 - 2015-05-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2015-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) AES Encryption Circuit against Clock Glitch based Fault Analysis 
Sub Title (in English)  
Keyword(1) advanced encryption standard  
Keyword(2) side-channel attacks  
Keyword(3) fault analysis  
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1st Author's Name Daisuke Hirano  
1st Author's Affiliation Waseda University (Waseda Univ)
2nd Author's Name Youhua Shi  
2nd Author's Affiliation Waseda University (Waseda Univ)
3rd Author's Name Nozomu Togawa  
3rd Author's Affiliation Waseda University (Waseda Univ)
4th Author's Name Masao Yanagisawa  
4th Author's Affiliation Waseda University (Waseda Univ)
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Speaker Author-1 
Date Time 2015-05-14 15:25:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2015-7 
Volume (vol) vol.115 
Number (no) no.21 
Page pp.51-55 
#Pages 5 
Date of Issue 2015-05-07 (VLD) 

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