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Paper Abstract and Keywords
Presentation 2015-06-20 11:10
A Rapid Verification Environment for Statistical Evaluation of PUF Circuits
Toshihiro Katashita, Yasunori Onda, Yohei Hori (AIST) RECONF2015-18
Abstract (in Japanese) (See Japanese page) 
(in English) In this study, we constructed a rapid experimentation environment for Physically Unclonable Function (PUF) circuit verification. PUF is significant technology for device authentication, cryptographic key generation and countermeasure against counterfeits. In the field of PUF studies, FPGA is effective for evaluation and comparison between architectures. However, many devices are required to extract PUF parameters for evaluation. Thus, several FPGA boards were used.
In this background, we developed an instrument and software that extracts PUF parameters from 120 FPGA devices automatically. In this paper, the structure and the procedure of testing are described, and the effectiveness is shown with preliminary experimentation using 100 devices.
Keyword (in Japanese) (See Japanese page) 
(in English) Physical Unclonable Function (PUF) / Pseudo LFSR PUF / Arbiter PUF / FPGA / Verification Environment / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 109, RECONF2015-18, pp. 97-102, June 2015.
Paper # RECONF2015-18 
Date of Issue 2015-06-12 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF RECONF2015-18

Conference Information
Committee RECONF  
Conference Date 2015-06-19 - 2015-06-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyoto University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) the 10th anniversary celebration of RECONF: Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2015-06-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Rapid Verification Environment for Statistical Evaluation of PUF Circuits 
Sub Title (in English)  
Keyword(1) Physical Unclonable Function (PUF)  
Keyword(2) Pseudo LFSR PUF  
Keyword(3) Arbiter PUF  
Keyword(4) FPGA  
Keyword(5) Verification Environment  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Toshihiro Katashita  
1st Author's Affiliation Advanced Industrial Science and Technology (AIST)
2nd Author's Name Yasunori Onda  
2nd Author's Affiliation Advanced Industrial Science and Technology (AIST)
3rd Author's Name Yohei Hori  
3rd Author's Affiliation Advanced Industrial Science and Technology (AIST)
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Speaker Author-1 
Date Time 2015-06-20 11:10:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2015-18 
Volume (vol) vol.115 
Number (no) no.109 
Page pp.97-102 
#Pages 6 
Date of Issue 2015-06-12 (RECONF) 

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