講演抄録/キーワード |
講演名 |
2015-06-20 09:55
A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications ○Vu Hoang Gia・Tran Thi Hong・Shinya Takamaeda・Yasuhiko Nakashima(NAIST) RECONF2015-15 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
Memory latency is the most serious design concern in computing centric architectures integrated with cache levels as a deep memory hierarchy. This latency directly decreases the computing speed while increases the energy consumption of such system in total. The impact is even more critical in intensive-data-movement applications, in which memory access completely dominates data processing in computing engines. To alleviate such latency, we propose an architecture which allows some computing functions to be executed near the memory. This architecture is also expected to exploit the advantages of non-cached computing models while able to combine with cached computing engines. |
キーワード |
(和) |
/ / / / / / / |
(英) |
Near data processing / near memory / near DRAM / memory latency / memory hierarchy / cache hierarchy / / |
文献情報 |
信学技報, vol. 115, no. 109, RECONF2015-15, pp. 79-84, 2015年6月. |
資料番号 |
RECONF2015-15 |
発行日 |
2015-06-12 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
査読に ついて |
本技術報告は査読を経ていない技術報告であり,推敲を加えられていずれかの場に発表されることがあります. |
PDFダウンロード |
RECONF2015-15 |