Paper Abstract and Keywords |
Presentation |
2015-06-20 09:55
A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications Vu Hoang Gia, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) RECONF2015-15 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Memory latency is the most serious design concern in computing centric architectures integrated with cache levels as a deep memory hierarchy. This latency directly decreases the computing speed while increases the energy consumption of such system in total. The impact is even more critical in intensive-data-movement applications, in which memory access completely dominates data processing in computing engines. To alleviate such latency, we propose an architecture which allows some computing functions to be executed near the memory. This architecture is also expected to exploit the advantages of non-cached computing models while able to combine with cached computing engines. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Near data processing / near memory / near DRAM / memory latency / memory hierarchy / cache hierarchy / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 109, RECONF2015-15, pp. 79-84, June 2015. |
Paper # |
RECONF2015-15 |
Date of Issue |
2015-06-12 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
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RECONF2015-15 |
Conference Information |
Committee |
RECONF |
Conference Date |
2015-06-19 - 2015-06-20 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kyoto University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
the 10th anniversary celebration of RECONF: Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2015-06-RECONF |
Language |
English |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications |
Sub Title (in English) |
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Keyword(1) |
Near data processing |
Keyword(2) |
near memory |
Keyword(3) |
near DRAM |
Keyword(4) |
memory latency |
Keyword(5) |
memory hierarchy |
Keyword(6) |
cache hierarchy |
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1st Author's Name |
Vu Hoang Gia |
1st Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
2nd Author's Name |
Tran Thi Hong |
2nd Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
3rd Author's Name |
Shinya Takamaeda |
3rd Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
4th Author's Name |
Yasuhiko Nakashima |
4th Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
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Speaker |
Author-1 |
Date Time |
2015-06-20 09:55:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2015-15 |
Volume (vol) |
vol.115 |
Number (no) |
no.109 |
Page |
pp.79-84 |
#Pages |
6 |
Date of Issue |
2015-06-12 (RECONF) |