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Paper Abstract and Keywords
Presentation 2015-07-21 14:55
A Circuit Implementation Technique for a Beta-A/D Converter with Unity-Gain Buffer
Fumiya Kawaguchi, Yoshihiko Horio (Tokyo Denki Univ.) NLP2015-70
Abstract (in Japanese) (See Japanese page) 
(in English) $beta$-A/D converter circuits based on the $beta$-map are robust against the fluctuations and mismatches in the constituent device characteristics, so that they are suitable for an IC implementation through advanced microfabrication semiconductor processes.
The integrated $beta$-A/D converters have shown their superior characteristics such as robustness, low-power, and small area.
In an ordinary binary A/D converter, a Unity-Gain Buffer (UGB) has been used to improve the conversion speed.
In this paper, we propose a circuit implementation technique for a $beta$-A/D converter citcuit with UGB in order to realize a high-speed, small, and low-power A/D converter.
In the circuits based on the UGBs, gain errors in the UGBs will be critical.
However, a high-performance $beta$-A/D converter circuit would be possible even with such gain errors, because the $beta$-A/D converter circuit is expected to be robust to the gain of the UGB.
We investigate the effects of the UGB gain on the conversion characteristics of the proposed $beta$-A/D converter circuits through SPICE and numerical simulations with C-language.
Keyword (in Japanese) (See Japanese page) 
(in English) A/D converter based on $beta$-map / Unity-gain buffer / A/D converter circuit / $beta$-transformation / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 150, NLP2015-70, pp. 17-21, July 2015.
Paper # NLP2015-70 
Date of Issue 2015-07-14 (NLP) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee NLP  
Conference Date 2015-07-21 - 2015-07-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Bibai Onsen Yu-rinkan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Nonlinear Problems, etc. 
Paper Information
Registration To NLP 
Conference Code 2015-07-NLP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Circuit Implementation Technique for a Beta-A/D Converter with Unity-Gain Buffer 
Sub Title (in English)  
Keyword(1) A/D converter based on $beta$-map  
Keyword(2) Unity-gain buffer  
Keyword(3) A/D converter circuit  
Keyword(4) $beta$-transformation  
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Keyword(6)  
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Keyword(8)  
1st Author's Name Fumiya Kawaguchi  
1st Author's Affiliation Tokyo Denki University (Tokyo Denki Univ.)
2nd Author's Name Yoshihiko Horio  
2nd Author's Affiliation Tokyo Denki University (Tokyo Denki Univ.)
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Speaker Author-1 
Date Time 2015-07-21 14:55:00 
Presentation Time 25 minutes 
Registration for NLP 
Paper # NLP2015-70 
Volume (vol) vol.115 
Number (no) no.150 
Page pp.17-21 
#Pages
Date of Issue 2015-07-14 (NLP) 


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