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Paper Abstract and Keywords
Presentation 2015-08-04 10:00
Design Space Exploration of Computational Photography Accelerator
Yuttakon Yuttakonkit, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-17
Abstract (in Japanese) (See Japanese page) 
(in English) Computational photography applications use image processing to extract quality improvement or addi- tional features. Instances of current implementation are refocusing and post-made depth of field for smartphones, optical manufacturing inspection for industrial. One key property of these applications is obtaining depth of objects from still image. Instead of using multiple cameras, a single 4D image that consists of collated micro images can directly extract the depth of objects by differentiating amongst multiple micro images. Though calculations inside a micro image is capable for parallelism but the far distance between comparison pair’s pixel on neighbor micro image is drastically obstruction. This Sparse Stencil memory access is the most hotspot for 4D image application’s algorithm. Recent mobile device especially smartphone also try to add 4D like’s features but obstructed with pro- cessing performance and also power consumption due to limited battery, thus either quality or resolution is too low. To overcome this, we proposed an accelerator, which operate along side with the main mobile processor. The appli- cations’s algorithm are analyzed, then we use conventional multicore processor simulator to conduct design space exploration. Result shows that, speed of cache is dominated the performance while size of cache is least effective. ROB size and amount of cores is the second priority. Furthermore by comparing the simulation with real hardware result, we found that not only parameters tuning on subject architectures but detail on internal architecture design is also essential to improve both performance and power efficiency.
Keyword (in Japanese) (See Japanese page) 
(in English) Architecture design / System design / Computational photography / Stencil application / Mobile Processor / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 174, CPSY2015-17, pp. 7-12, Aug. 2015.
Paper # CPSY2015-17 
Date of Issue 2015-07-28 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2015-17

Conference Information
Committee CPSY DC IPSJ-ARC  
Conference Date 2015-08-04 - 2015-08-06 
Place (in Japanese) (See Japanese page) 
Place (in English) B-Con Plaza (Beppu) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing 
Paper Information
Registration To CPSY 
Conference Code 2015-08-CPSY-DC-ARC 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design Space Exploration of Computational Photography Accelerator 
Sub Title (in English)  
Keyword(1) Architecture design  
Keyword(2) System design  
Keyword(3) Computational photography  
Keyword(4) Stencil application  
Keyword(5) Mobile Processor  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yuttakon Yuttakonkit  
1st Author's Affiliation Nara Institute of Science and Techonology (NAIST)
2nd Author's Name Tran Thi Hong  
2nd Author's Affiliation Nara Institute of Science and Techonology (NAIST)
3rd Author's Name Shinya Takamaeda  
3rd Author's Affiliation Nara Institute of Science and Techonology (NAIST)
4th Author's Name Yasuhiko Nakashima  
4th Author's Affiliation Nara Institute of Science and Techonology (NAIST)
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Speaker Author-1 
Date Time 2015-08-04 10:00:00 
Presentation Time 30 minutes 
Registration for CPSY 
Paper # CPSY2015-17 
Volume (vol) vol.115 
Number (no) no.174 
Page pp.7-12 
#Pages
Date of Issue 2015-07-28 (CPSY) 


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