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| Presentation | 2015-10-26 15:25 A Power-Efficient Memory Hierarchy Design for the 3D Integration Era Wataru Uno, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.)  VLD2015-30 ICD2015-43 IE2015-65 Link to ES Tech. Rep. Archives: ICD2015-43 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | 3D-stacked memories are expected to play key roles to realize high-performance and low-power computing systems. This paper examines various computing systems including a 3D-stacked main memory and two- or three-level cache hierarchies. From the evaluation results, it is observed that cache hierarchy has an impact on the power efficiency of the memory subsystem with a 3D-stacked main memory. In addition, to judge the effectiveness of the L3 cache in improving power efficiency of the computing system including a 3D-stacked main memory, this paper examines two metrics of application characteristics, Miss Per Kilo-Instruction (MPKI) on the L2 caches and an MPKI reduction rate by employing the L3 cache. These metrics have potentials to clarify the best configuration of cache hierarchy that can maximize power efficiency of the computing system including a 3D-stacked main memory. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | stacked memory / 3D-IC / memory hierarchy / memory system / cache / computing system / computer architecture / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 271, ICD2015-43, pp. 19-24, Oct. 2015. | |
| Paper # | ICD2015-43 | |
| Date of Issue | 2015-10-19 (VLD, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2015-30 ICD2015-43 IE2015-65 Link to ES Tech. Rep. Archives: ICD2015-43 |
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| Conference Information | |
| Committee | ICD IE VLD IPSJ-SLDM |
| Conference Date | 2015-10-26 - 2015-10-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2015-10-ICD-IE-VLD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Power-Efficient Memory Hierarchy Design for the 3D Integration Era |
| Sub Title (in English) | |
| Keyword(1) | stacked memory |
| Keyword(2) | 3D-IC |
| Keyword(3) | memory hierarchy |
| Keyword(4) | memory system |
| Keyword(5) | cache |
| Keyword(6) | computing system |
| Keyword(7) | computer architecture |
| Keyword(8) | |
| 1st Author's Name | Wataru Uno |
| 1st Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 2nd Author's Name | Masayuki Sato |
| 2nd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 3rd Author's Name | Ryusuke Egawa |
| 3rd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 4th Author's Name | Hiroaki Kobayashi |
| 4th Author's Affiliation | Tohoku University (Tohoku Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-10-26 15:25:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | VLD2015-30, ICD2015-43, IE2015-65 |
| Volume (vol) | vol.115 |
| Number (no) | no.270(VLD), no.271(ICD), no.272(IE) |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2015-10-19 (VLD, ICD, IE) |
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