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Paper Abstract and Keywords
Presentation 2015-12-03 10:10
A Quantitative Criterion of Gate-Level Netlist Vulnerability
Masaru Oya, Youhua Shi (Waseda Univ.), Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-59 DC2015-55
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry.
This circumstance introduces risks implemented Hardware Trojans(HTs) by malicious attackers.
This paper proposes an HT rank which is a new analysis criterion
against HTs at gate-level netlists. The HT rank does not use any
simulation tools but just calculate Trojan points based on Trojan net
features. The HT rank successfully classifies all the gate-level
netlists in Trust-HUB, ISCAS85, ISCAS89, and ITC99 as well as several
OpenCores designs, HT-free and HT-inserted AES
netlists into HT-inserted ones and HT-free ones.
We took approximately several minutes to one day depending on
a netlist to calculate an HT rank using Xeon E7-4870.
Keyword (in Japanese) (See Japanese page) 
(in English) hardware Trojan / gate-level netlist / design phase / Trojan net / Trojan point / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 338, VLD2015-59, pp. 141-146, Dec. 2015.
Paper # VLD2015-59 
Date of Issue 2015-11-24 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2015-59 DC2015-55

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Quantitative Criterion of Gate-Level Netlist Vulnerability 
Sub Title (in English)  
Keyword(1) hardware Trojan  
Keyword(2) gate-level netlist  
Keyword(3) design phase  
Keyword(4) Trojan net  
Keyword(5) Trojan point  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Masaru Oya  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Youhua Shi  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Noritaka Yamashita  
3rd Author's Affiliation NEC Corporation (NEC)
4th Author's Name Toshihiko Okamura  
4th Author's Affiliation NEC Corporation (NEC)
5th Author's Name Yukiyasu Tsunoo  
5th Author's Affiliation NEC Corporation (NEC)
6th Author's Name Masao Yanagisawa  
6th Author's Affiliation Waseda University (Waseda Univ.)
7th Author's Name Nozomu Togawa  
7th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2015-12-03 10:10:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2015-59, DC2015-55 
Volume (vol) vol.115 
Number (no) no.338(VLD), no.339(DC) 
Page pp.141-146 
#Pages 6 
Date of Issue 2015-11-24 (VLD, DC) 

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