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Paper Abstract and Keywords
Presentation 2015-12-14 11:30
Memory Application of Ultrafine FET utilizing Supramolecular Protein
Takahiko Ban, Mutsunori Uenuma (NAIST), Shinji Migita (AIST), Yasuaki Ishikawa, Ichiro Yamashita, Yukiharu Uraoka (NAIST) EID2015-11 SDM2015-94
Abstract (in Japanese) (See Japanese page) 
(in English) Metal nanoparticles (NPs) embedded in junctionless field-effect transistors (JL-FETs) with a length of 3.6 nm is fabricated and demonstrated. The anisotropic wet etching of a silicon-on-insulator (SOI) substrate was utilized to form V-grooves and to define nanometer-scale channel. Metal NPs are selectively placed onto bottom of V-groove using the Baio nano process (BNP). The JL-FET is applied to floating gate memory and used to investigate an impact on the short channel by charge trap of NPs. Low-voltage operation and broad threshold voltage shift as memory behavior are appeared in 3.6 nm channel length. It is expected that the JL-FETs can overcome the scaling limitations in floating gate memory, while the charge trap cause major problems in the sub 10 nm region.
Keyword (in Japanese) (See Japanese page) 
(in English) Bio Nano Process / Junctionless-FET / Nano-particle / Memory / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 362, EID2015-11, pp. 9-12, Dec. 2015.
Paper # EID2015-11 
Date of Issue 2015-12-07 (EID, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF EID2015-11 SDM2015-94

Conference Information
Committee EID SDM  
Conference Date 2015-12-14 - 2015-12-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Ryukoku University, Avanti Kyoto Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Si and Si-related Materials and Devices, and Display Technology 
Paper Information
Registration To EID 
Conference Code 2015-12-EID-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Memory Application of Ultrafine FET utilizing Supramolecular Protein 
Sub Title (in English)  
Keyword(1) Bio Nano Process  
Keyword(2) Junctionless-FET  
Keyword(3) Nano-particle  
Keyword(4) Memory  
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Keyword(6)  
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1st Author's Name Takahiko Ban  
1st Author's Affiliation Nara Insutitute of Science and Technology (NAIST)
2nd Author's Name Mutsunori Uenuma  
2nd Author's Affiliation Nara Insutitute of Science and Technology (NAIST)
3rd Author's Name Shinji Migita  
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
4th Author's Name Yasuaki Ishikawa  
4th Author's Affiliation Nara Insutitute of Science and Technology (NAIST)
5th Author's Name Ichiro Yamashita  
5th Author's Affiliation Nara Insutitute of Science and Technology (NAIST)
6th Author's Name Yukiharu Uraoka  
6th Author's Affiliation Nara Insutitute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2015-12-14 11:30:00 
Presentation Time 15 minutes 
Registration for EID 
Paper # EID2015-11, SDM2015-94 
Volume (vol) vol.115 
Number (no) no.362(EID), no.363(SDM) 
Page pp.9-12 
#Pages 4 
Date of Issue 2015-12-07 (EID, SDM) 

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