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Paper Abstract and Keywords
Presentation 2015-12-18 14:00
Error Correcting Codes Considering P/E Cycles for NAND Flash Memories
Mampei Asai, Masato Kitakami (Chiba Univ.) DC2015-76
Abstract (in Japanese) (See Japanese page) 
(in English) I Recently, multi-level cell (MLC) NAND flash memory, which has memory cells capable to store 2 or more bits of information, is widely used in order to achieve high memory density. Since the dominant error in the MLC NAND flash memory is unidirectional 1-level error, a code which can correct such errors has been proposed. In NAND flash memory, erase operation is necessary before program (writing) operation. This continuous erase - program operation is called P/E cycle. As the number of P/E operations increases, the probability of multiple symbol error cannot be neglectable. The unidirectional 1-level error correcting code cannot correct these errors. This paper proposes an error correcting method which counts the number of P/E cycles of each memory cell. The proposed method applies unidirectional 1-level error correcting code at first; and applies multi symbol error correcting code if the number of P/E cycles exceeds the predetermined value. Evaluation shows that the proposed method can switch error correcting code maintaining low error rate of the decoded data.
Keyword (in Japanese) (See Japanese page) 
(in English) NAND Flash Memory / Error Correcting Code / P/E Cycle / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 382, DC2015-76, pp. 17-22, Dec. 2015.
Paper # DC2015-76 
Date of Issue 2015-12-11 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2015-12-18 - 2015-12-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Kurieito Mulakami (Murakami City) 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2015-12-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Error Correcting Codes Considering P/E Cycles for NAND Flash Memories 
Sub Title (in English)  
Keyword(1) NAND Flash Memory  
Keyword(2) Error Correcting Code  
Keyword(3) P/E Cycle  
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1st Author's Name Mampei Asai  
1st Author's Affiliation Chiba University (Chiba Univ.)
2nd Author's Name Masato Kitakami  
2nd Author's Affiliation Chiba University (Chiba Univ.)
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Speaker Author-1 
Date Time 2015-12-18 14:00:00 
Presentation Time 20 minutes 
Registration for DC 
Paper # DC2015-76 
Volume (vol) vol.115 
Number (no) no.382 
Page pp.17-22 
#Pages 6 
Date of Issue 2015-12-11 (DC) 

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