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Paper Abstract and Keywords
Presentation 2016-01-20 14:15
Design of Stencil Computation based on Building-Cube Method on an FPGA Accelerator with High Level Synthesis
Rie Soejima, Koji Okina, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2015-91 CPSY2015-123 RECONF2015-73
Abstract (in Japanese) (See Japanese page) 
(in English) In building-cube method (BCM), which is one of the adaptive mesh refinement, the computational region is divided into a number of sub-domains with various sizes. One of advantages of the BCM that it suits parallel processing, due to each sub-domain has a similar data size and a similar computing flow in spite of the difference in size. This paper presents implementation of a class library framework on a high-level synthesis system, which aims at enabling easy FPGA implementation of BCM-based stencil computation. The proposed framework is evaluated with a heat conduction simulation as a benchmark application in terms of computing performance, memory performance and hardware amount, so that overheads of a mechanism of data exchange between sub-domains with different size are revealed.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Stencil computation / Building-cube method / High level synthesis tool / MaxCompiler / Heat conduction simulation / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 400, RECONF2015-73, pp. 125-130, Jan. 2016.
Paper # RECONF2015-73 
Date of Issue 2016-01-12 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2015-91 CPSY2015-123 RECONF2015-73

Conference Information
Committee VLD CPSY RECONF IPSJ-SLDM IPSJ-ARC  
Conference Date 2016-01-19 - 2016-01-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2016-01-VLD-CPSY-RECONF-SLDM-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of Stencil Computation based on Building-Cube Method on an FPGA Accelerator with High Level Synthesis 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Stencil computation  
Keyword(3) Building-cube method  
Keyword(4) High level synthesis tool  
Keyword(5) MaxCompiler  
Keyword(6) Heat conduction simulation  
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Keyword(8)  
1st Author's Name Rie Soejima  
1st Author's Affiliation Nagasaki University (Nagasaki Univ.)
2nd Author's Name Koji Okina  
2nd Author's Affiliation Nagasaki University (Nagasaki Univ.)
3rd Author's Name Yuichiro Shibata  
3rd Author's Affiliation Nagasaki University (Nagasaki Univ.)
4th Author's Name Kiyoshi Oguri  
4th Author's Affiliation Nagasaki University (Nagasaki Univ.)
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Speaker Author-1 
Date Time 2016-01-20 14:15:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2015-91, CPSY2015-123, RECONF2015-73 
Volume (vol) vol.115 
Number (no) no.398(VLD), no.399(CPSY), no.400(RECONF) 
Page pp.125-130 
#Pages 6 
Date of Issue 2016-01-12 (VLD, CPSY, RECONF) 

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