Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2016-02-17 16:05
Study on the Effect of Power Supply Noise on Flip-Flop Circuits
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.) DC2015-96
Abstract (in Japanese) (See Japanese page) 
(in English) According to the scaling down, and lower power design of VLSI circuits, power supply noise such as IR-drop affects the operation of memory cells such as SRAM and FF circuits. Error occurrence on SRAM is already reported and some countermeasures are proposed. It is likely that further scaling down and lower power design will cause the error similar to that on SRAM for FF circuits and countermeasures will be needed. In this paper, we analyzed the effect of power supply noise on FF circuits and considered the cause of error occurrence.
Keyword (in Japanese) (See Japanese page) 
(in English) Power Supply Noise / Flip-Flop / Latch / Bit-Flip / Malfunction / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 449, DC2015-96, pp. 61-66, Feb. 2016.
Paper # DC2015-96 
Date of Issue 2016-02-10 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2015-96

Conference Information
Committee DC  
Conference Date 2016-02-17 - 2016-02-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2016-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study on the Effect of Power Supply Noise on Flip-Flop Circuits 
Sub Title (in English)  
Keyword(1) Power Supply Noise  
Keyword(2) Flip-Flop  
Keyword(3) Latch  
Keyword(4) Bit-Flip  
Keyword(5) Malfunction  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Takuya Yamamoto  
1st Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
2nd Author's Name Yukiya Miura  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2016-02-17 16:05:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2015-96 
Volume (vol) vol.115 
Number (no) no.449 
Page pp.61-66 
#Pages 6 
Date of Issue 2016-02-10 (DC) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan