Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2016-03-22 11:00
An STDP control circuit and its evaluation using a Cu-MoOx-Al resistance change memory fabricated on a Si MOSFET
Kazumasa Tomizaki, Takashi Morie, Hideyuki Ando (Kyushu Inst. Tech.), Atsushi Fukuchi, Masashi Arita, Yasuo Takahashi (Hokkaido Univ.) NC2015-70
Abstract (in Japanese) (See Japanese page) 
(in English) With the progress of practical implementation of deep learning in neural networks, high-speed and low-power neural hardware (very-large-scale integrated circuits) that performs learning operation is being developed. The circuit architecture of such hardware is classified into digital and analog. Several digital neural integrated circuits have already been developed, and analog neural integrated circuits, which are expected to achieve higher performance, are also being developed. The most crucial issue for analog neural circuits is development of analog memory devices. Recently, as promising such devices, resistance change memory devices are actively studied, and some analog neural circuits with learning mechanisms using such devices have been reported. Spike-timing dependent plasticity (STDP) is often tried to implement as a learning rule. In this paper, we report evaluation results of analog memory characteristics of resistance change memory devices including Molybdenum oxide, design of memory control circuits implementing STDP, and experimental results of memory operation with asymmetric STDP characteristics.
Keyword (in Japanese) (See Japanese page) 
(in English) resistance change memory / neural network hardware / STDP control circuit / SET/RESET operation / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 514, NC2015-70, pp. 7-12, March 2016.
Paper # NC2015-70 
Date of Issue 2016-03-15 (NC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NC2015-70

Conference Information
Committee MBE NC  
Conference Date 2016-03-22 - 2016-03-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Tamagawa University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To NC 
Conference Code 2016-03-MBE-NC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An STDP control circuit and its evaluation using a Cu-MoOx-Al resistance change memory fabricated on a Si MOSFET 
Sub Title (in English)  
Keyword(1) resistance change memory  
Keyword(2) neural network hardware  
Keyword(3) STDP control circuit  
Keyword(4) SET/RESET operation  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Kazumasa Tomizaki  
1st Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. Tech.)
2nd Author's Name Takashi Morie  
2nd Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. Tech.)
3rd Author's Name Hideyuki Ando  
3rd Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. Tech.)
4th Author's Name Atsushi Fukuchi  
4th Author's Affiliation Hokkaido University (Hokkaido Univ.)
5th Author's Name Masashi Arita  
5th Author's Affiliation Hokkaido University (Hokkaido Univ.)
6th Author's Name Yasuo Takahashi  
6th Author's Affiliation Hokkaido University (Hokkaido Univ.)
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2016-03-22 11:00:00 
Presentation Time 25 minutes 
Registration for NC 
Paper # NC2015-70 
Volume (vol) vol.115 
Number (no) no.514 
Page pp.7-12 
#Pages 6 
Date of Issue 2016-03-15 (NC) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan