| Paper Abstract and Keywords |
| Presentation |
2016-04-14 15:15
[Invited Lecture]
1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Tosinari Watanabe, Hideo Sato, Soshi Sato, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Takaho Tanigawa, Masaaki Niwa, Kenchi Ito, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2016-10 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array with a high-signal-margin reference generator circuit was developed to achieve high-density 1T1MTJ STT-MRAMs. Fluctuations in the memory cell characteristics were first measured using a 1-kbit STT-MRAM test chip. Based on these measurements, a reference generator and an STT-MRAM cell array architecture were proposed. This cell array was evaluated in terms of the signal margin for read operation by means of Monte-Carlo SPICE circuit simulations. The proposed design enables a 50% improvement in the signal margin compared with the conventional cell array circuit. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
STT-MRAM / sense amplifier / reference / array / Monte-Carlo simulation / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 116, no. 3, ICD2016-10, pp. 51-56, April 2016. |
| Paper # |
ICD2016-10 |
| Date of Issue |
2016-04-07 (ICD) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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| Download PDF |
ICD2016-10 |