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Paper Abstract and Keywords
Presentation 2016-05-11 15:20
MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA
Xushen Han, Dajiang Zhou, Shinji Kimura (Waseda Univ.) VLD2016-5
Abstract (in Japanese) (See Japanese page) 
(in English) Convolutional neural network has been paid so much attention in many intelligent applications especially image pattern recognition. Nowadays lots of high-throughput implementations are developed for acceleration of convolutional neural network, however, memory traffic has been the bottleneck if more resources are distributed on chip. In this paper we present MERP-CNN, a memory-efficient processor for both forward and backward propagation of convolutional neural networks. We implement our processor on Xilinx Vertex 7 FPGA platform. Our memory efficiency is 35.6% less than recent previous works. We also have a 279GFlops throughput for acceleration and not bad power performance. We take advantage of the multiboot specialty to keep top performance of our hardware resources.
Keyword (in Japanese) (See Japanese page) 
(in English) convolutional neural network / memory-efficient / multiboot / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 21, VLD2016-5, pp. 47-52, May 2016.
Paper # VLD2016-5 
Date of Issue 2016-05-04 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-5

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2016-05-11 - 2016-05-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2016-05-VLD-SLDM 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA 
Sub Title (in English)  
Keyword(1) convolutional neural network  
Keyword(2) memory-efficient  
Keyword(3) multiboot  
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1st Author's Name Xushen Han  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Dajiang Zhou  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Shinji Kimura  
3rd Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2016-05-11 15:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2016-5 
Volume (vol) vol.116 
Number (no) no.21 
Page pp.47-52 
#Pages 6 
Date of Issue 2016-05-04 (VLD) 

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