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Paper Abstract and Keywords
Presentation 2016-05-19 10:25
Design of an FPGA Platform for Stencil Computation Using OpenCL
Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.) RECONF2016-3
Abstract (in Japanese) (See Japanese page) 
(in English) Stencil computation is widely used in scientific computations. Its processing speed is usually restricted by the external memory bandwidth.
FPGAs have solve this problem by utilizing large internal memory efficiently.
However, a very large design time and hardware design skills are required to implement an FPGA architecture successfully.
To solve this problem, we propose an FPGA platform, designed entirely using C-like programming language called OpenCL (open computing language).
According to the experimental results, we achieved 100~200 GFLOPS of processing speed.
Keyword (in Japanese) (See Japanese page) 
(in English) Stencil computation / iterative computation / accelerator / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 53, RECONF2016-3, pp. 9-12, May 2016.
Paper # RECONF2016-3 
Date of Issue 2016-05-12 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2016-3

Conference Information
Committee RECONF  
Conference Date 2016-05-19 - 2016-05-20 
Place (in Japanese) (See Japanese page) 
Place (in English) FUJITSU LAB. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2016-05-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of an FPGA Platform for Stencil Computation Using OpenCL 
Sub Title (in English)  
Keyword(1) Stencil computation  
Keyword(2) iterative computation  
Keyword(3) accelerator  
Keyword(4) FPGA  
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1st Author's Name Hasitha Muthumala Waidyasooriya  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Masanori Hariyama  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2016-05-19 10:25:00 
Presentation Time 20 minutes 
Registration for RECONF 
Paper # RECONF2016-3 
Volume (vol) vol.116 
Number (no) no.53 
Page pp.9-12 
#Pages 4 
Date of Issue 2016-05-12 (RECONF) 

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