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| Presentation | 2016-06-17 16:10 Tamper Resistant Asynchronous Pipeline Circuits using Random Delay Elements Daiki Toyoshima, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.)  CAS2016-34 VLD2016-40 SIP2016-68 MSS2016-34 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Asynchronous bundled-data transfer circuits use delay elements as a strobe signal which indicates the stable state of the corresponding combinational circuit. Its delay value is always larger than that of the critical path in the combinational circuit. If it is constant as well as the clock signal of synchronous circuits, the current and the electromagnetic wave of the target devices show the same characteristics when they perform the same functions. Thus, they cannot tolerate side channel attacks. On the other hand, their characteristics can be varied by using random delay elements even if they perform the same functions. In this paper, we propose the circuit structure of random delay elements and present tamper-resistant asynchronous circuits. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Random delay element / Tamper resistant / Bundled-data / Side-channel attack / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 94, VLD2016-40, pp. 185-190, June 2016. | |
| Paper # | VLD2016-40 | |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2016-34 VLD2016-40 SIP2016-68 MSS2016-34 |
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| Conference Information | |
| Committee | VLD CAS MSS SIP |
| Conference Date | 2016-06-16 - 2016-06-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hirosaki Shiritsu Kanko-kan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System, signal processing and related topics |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2016-06-VLD-CAS-MSS-SIP |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Tamper Resistant Asynchronous Pipeline Circuits using Random Delay Elements |
| Sub Title (in English) | |
| Keyword(1) | Random delay element |
| Keyword(2) | Tamper resistant |
| Keyword(3) | Bundled-data |
| Keyword(4) | Side-channel attack |
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| 1st Author's Name | Daiki Toyoshima |
| 1st Author's Affiliation | Hirosaki University (Hirosaki Univ.) |
| 2nd Author's Name | Atsushi Kurokawa |
| 2nd Author's Affiliation | Hirosaki University (Hirosaki Univ.) |
| 3rd Author's Name | Masashi Imai |
| 3rd Author's Affiliation | Hirosaki University (Hirosaki Univ.) |
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| Speaker | Author-1 |
| Date Time | 2016-06-17 16:10:00 |
| Presentation Time | 20 minutes |
| Registration for | VLD |
| Paper # | CAS2016-34, VLD2016-40, SIP2016-68, MSS2016-34 |
| Volume (vol) | vol.116 |
| Number (no) | no.93(CAS), no.94(VLD), no.95(SIP), no.96(MSS) |
| Page | pp.185-190 |
| #Pages | 6 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |
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