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Paper Abstract and Keywords
Presentation 2016-06-17 09:50
Design and Evaluation of MTJ-based Standard Cell Memory
Junya Akaike, Masaru Kudo, Kimiyoshi Usami (SIT) CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19
Abstract (in Japanese) (See Japanese page) 
(in English) With the spread of portable devices, products with high performance and long battery life are required. In this paper, we propose a Magnetic Tunnel Junction (MTJ)-based Standard Cell Memory (SCM) to reduce the power consumption of the cache memory. Simulation results showed that SCM can operate at a low voltage and has a high effectiveness in power reduction by PG.
Keyword (in Japanese) (See Japanese page) 
(in English) Power-Gating / MTJ / Standard Cell Memory / Break-Even Time / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 94, VLD2016-25, pp. 103-108, June 2016.
Paper # VLD2016-25 
Date of Issue 2016-06-09 (CAS, VLD, SIP, MSS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19

Conference Information
Committee VLD CAS MSS SIP  
Conference Date 2016-06-16 - 2016-06-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hirosaki Shiritsu Kanko-kan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System, signal processing and related topics 
Paper Information
Registration To VLD 
Conference Code 2016-06-VLD-CAS-MSS-SIP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and Evaluation of MTJ-based Standard Cell Memory 
Sub Title (in English)  
Keyword(1) Power-Gating  
Keyword(2) MTJ  
Keyword(3) Standard Cell Memory  
Keyword(4) Break-Even Time  
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1st Author's Name Junya Akaike  
1st Author's Affiliation Shibaura Institute of Technology (SIT)
2nd Author's Name Masaru Kudo  
2nd Author's Affiliation Shibaura Institute of Technology (SIT)
3rd Author's Name Kimiyoshi Usami  
3rd Author's Affiliation Shibaura Institute of Technology (SIT)
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Speaker Author-1 
Date Time 2016-06-17 09:50:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # CAS2016-19, VLD2016-25, SIP2016-53, MSS2016-19 
Volume (vol) vol.116 
Number (no) no.93(CAS), no.94(VLD), no.95(SIP), no.96(MSS) 
Page pp.103-108 
#Pages 6 
Date of Issue 2016-06-09 (CAS, VLD, SIP, MSS) 

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