Paper Abstract and Keywords |
Presentation |
2016-06-17 10:30
An FPGA Implementation of Real-time Optical Flow Estimation Processor Yu Suzuki, Masato Ito, Satoshi Kanda, Tetsuya Matsumura (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.) CAS2016-21 VLD2016-27 SIP2016-55 MSS2016-21 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A real-time optical flow processor has been implemented using single FPGA chip. By introducing four effective methods, modified newton’s method, hierarchical SOR method, modified initial flow generation method, and optimization of overlap pixels, both reducing the hardware amount and improving the flow accuracy are accomplished. Also by introducing the pipeline structure to this processor, high through-put hardware implementation can be realized. Total LC amount and memory capacity of this processor are reduced about 8% and 16% respectively compared to previous our HOE processor. This processor performs WXGA 30-fps at 175.5MHz real-time optical flow processing with single FPGA. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Optical flow / HOE / Newton's method / SOR method / Processor / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 94, VLD2016-27, pp. 115-120, June 2016. |
Paper # |
VLD2016-27 |
Date of Issue |
2016-06-09 (CAS, VLD, SIP, MSS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2016-21 VLD2016-27 SIP2016-55 MSS2016-21 |
Conference Information |
Committee |
VLD CAS MSS SIP |
Conference Date |
2016-06-16 - 2016-06-17 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hirosaki Shiritsu Kanko-kan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System, signal processing and related topics |
Paper Information |
Registration To |
VLD |
Conference Code |
2016-06-VLD-CAS-MSS-SIP |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An FPGA Implementation of Real-time Optical Flow Estimation Processor |
Sub Title (in English) |
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Keyword(1) |
Optical flow |
Keyword(2) |
HOE |
Keyword(3) |
Newton's method |
Keyword(4) |
SOR method |
Keyword(5) |
Processor |
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1st Author's Name |
Yu Suzuki |
1st Author's Affiliation |
Nihon University (Nihon Univ.) |
2nd Author's Name |
Masato Ito |
2nd Author's Affiliation |
Nihon University (Nihon Univ.) |
3rd Author's Name |
Satoshi Kanda |
3rd Author's Affiliation |
Nihon University (Nihon Univ.) |
4th Author's Name |
Tetsuya Matsumura |
4th Author's Affiliation |
Nihon University (Nihon Univ.) |
5th Author's Name |
Kousuke Imamura |
5th Author's Affiliation |
Kanazawa University (Kanazawa Univ.) |
6th Author's Name |
Yoshio Matsuda |
6th Author's Affiliation |
Kanazawa University (Kanazawa Univ.) |
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Speaker |
Author-1 |
Date Time |
2016-06-17 10:30:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
CAS2016-21, VLD2016-27, SIP2016-55, MSS2016-21 |
Volume (vol) |
vol.116 |
Number (no) |
no.93(CAS), no.94(VLD), no.95(SIP), no.96(MSS) |
Page |
pp.115-120 |
#Pages |
6 |
Date of Issue |
2016-06-09 (CAS, VLD, SIP, MSS) |
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