| Paper Abstract and Keywords |
| Presentation |
2016-10-26 15:30
[Invited Talk]
Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB CMOS Circuits at Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi (Renesas Electronics Corp.), Nobuyuki Sugii (Hitach), Koichiro Ishibashi (The Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (The Univ. of Tokyo) SDM2016-71 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
SOTB / SOI / back bias / ring oscillator / Tpd / variability / ultra-low voltage / |
| Reference Info. |
IEICE Tech. Rep., vol. 116, no. 270, SDM2016-71, pp. 15-20, Oct. 2016. |
| Paper # |
SDM2016-71 |
| Date of Issue |
2016-10-19 (SDM) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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| Download PDF |
SDM2016-71 |