Paper Abstract and Keywords |
Presentation |
2016-11-28 13:35
Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA Manri Terada, Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-48 DC2016-42 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, the logic circuits are implemented to FPGA in many fields.
To achieve faster circuits, a design flow to implement general-synchronous circuits that allow to distribute the clock signal at different timings to the registers in FPGA produced by Xilinx has been proposed.However, since the excess margins are often added to work the general-synchronous circuits correctly in the existing method, the performance improvement by the existing method is not enough.Furthermore, in the existing method, since circuits given as the inputs of the flow are represented in gate-level, it is not practical.In this paper, to improve the existing method, we propose a design flow to implement the general-synchronous circuits to FPGA produced by Xilinx by using the engineering change order without adding the excess margins from the RTL representation.Experiment shows the effectiveness of the proposed method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Xilinx FPGA / engineering change order / general-synchronous framework / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 330, VLD2016-48, pp. 25-30, Nov. 2016. |
Paper # |
VLD2016-48 |
Date of Issue |
2016-11-21 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2016-48 DC2016-42 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE |
Conference Date |
2016-11-28 - 2016-11-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Ritsumeikan University, Osaka Ibaraki Campus |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2016 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA |
Sub Title (in English) |
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Keyword(1) |
Xilinx FPGA |
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engineering change order |
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general-synchronous framework |
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1st Author's Name |
Manri Terada |
1st Author's Affiliation |
The University of Aizu (Univ. of Aizu) |
2nd Author's Name |
Hayato Mashiko |
2nd Author's Affiliation |
The University of Aizu (Univ. of Aizu) |
3rd Author's Name |
Yukihide Kohira |
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The University of Aizu (Univ. of Aizu) |
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Speaker |
Author-1 |
Date Time |
2016-11-28 13:35:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2016-48, DC2016-42 |
Volume (vol) |
vol.116 |
Number (no) |
no.330(VLD), no.331(DC) |
Page |
pp.25-30 |
#Pages |
6 |
Date of Issue |
2016-11-21 (VLD, DC) |
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