IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2016-11-28 15:30
Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process
Michitarou Yabuuchi, Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Jun Furuta (KIT), Pieter Weckx (KUL/IMEC), Ben Kaczer (IMEC), Takashi Matsumoto (Univ. of Tokyo), Hidetoshi Onodera (Kyoto Univ.) VLD2016-52 DC2016-46
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a circuit analysis method using the bimodal RTN (random telegraph
noise) model of the defect-centric distribution. The conventional unimodal
model fails to replicate the effect of RTN on 40 nm SiON process
circuits. The bimodal model takes into account
defect characteristics of both HK and interface layer in
gate dielectric. The proposed method estimates defect
characteristics and reproduces frequency distributions by
RTN. We confirm the bimodal model fully
replicates the effect of RTN by comparing simulation and
measurement results of 40 nm test chips.
Keyword (in Japanese) (See Japanese page) 
(in English) RTN (Random Telegraph Noise) / defect-centric distribution / variation / reliability / circuit design / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 330, VLD2016-52, pp. 49-54, Nov. 2016.
Paper # VLD2016-52 
Date of Issue 2016-11-21 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-52 DC2016-46

Conference Information
Conference Date 2016-11-28 - 2016-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Ritsumeikan University, Osaka Ibaraki Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2016 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process 
Sub Title (in English)  
Keyword(1) RTN (Random Telegraph Noise)  
Keyword(2) defect-centric distribution  
Keyword(3) variation  
Keyword(4) reliability  
Keyword(5) circuit design  
1st Author's Name Michitarou Yabuuchi  
1st Author's Affiliation Kyoto Institute of Technology (KIT)
2nd Author's Name Azusa Oshima  
2nd Author's Affiliation Kyoto Institute of Technology (KIT)
3rd Author's Name Takuya Komawaki  
3rd Author's Affiliation Kyoto Institute of Technology (KIT)
4th Author's Name Kazutoshi Kobayashi  
4th Author's Affiliation Kyoto Institute of Technology (KIT)
5th Author's Name Ryo Kishida  
5th Author's Affiliation Kyoto Institute of Technology (KIT)
6th Author's Name Jun Furuta  
6th Author's Affiliation Kyoto Institute of Technology (KIT)
7th Author's Name Pieter Weckx  
7th Author's Affiliation KU Leuven/Interuniversity Microelectronics Centre (KUL/IMEC)
8th Author's Name Ben Kaczer  
8th Author's Affiliation Interuniversity Microelectronics Centre (IMEC)
9th Author's Name Takashi Matsumoto  
9th Author's Affiliation University of Tokyo (Univ. of Tokyo)
10th Author's Name Hidetoshi Onodera  
10th Author's Affiliation Kyoto University (Kyoto Univ.)
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2016-11-28 15:30:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2016-52, DC2016-46 
Volume (vol) vol.116 
Number (no) no.330(VLD), no.331(DC) 
Page pp.49-54 
Date of Issue 2016-11-21 (VLD, DC) 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan