| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2016-11-28 15:30 Hardware implementation of PLC Instructions by high level synthesis Ishigaki Yoshiki, Tanaka Tasuku, Fujieda Naoki, Ichikawa Shuichi (TUT)  RECONF2016-43 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The hardware implementation of instruction sequence is a method to conceal and to protect the intellectual property. In this study, PLC instructions are synthesized, implemented, and evaluated with Xilinx FPGA and Vivado HLS. The derived designs can be controlled by the directives of Vivado HLS. The reduction of latency was maximally 2% with pipelining, while the logic scale was reduced to 56% of the original by sharing arithmetic units. |
|
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Programmable Logic Controller / High Level Synthesis / Hardware Implementation / FPGA / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 332, RECONF2016-43, pp. 19-24, Nov. 2016. | |
| Paper # | RECONF2016-43 | |
| Date of Issue | 2016-11-21 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2016-43 |
|
| Conference Information | |
| Committee | VLD DC CPSY RECONF CPM ICD IE |
| Conference Date | 2016-11-28 - 2016-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware implementation of PLC Instructions by high level synthesis |
| Sub Title (in English) | |
| Keyword(1) | Programmable Logic Controller |
| Keyword(2) | High Level Synthesis |
| Keyword(3) | Hardware Implementation |
| Keyword(4) | FPGA |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ishigaki Yoshiki |
| 1st Author's Affiliation | toyohashi university of technology (TUT) |
| 2nd Author's Name | Tanaka Tasuku |
| 2nd Author's Affiliation | toyohashi university of technology (TUT) |
| 3rd Author's Name | Fujieda Naoki |
| 3rd Author's Affiliation | toyohashi university of technology (TUT) |
| 4th Author's Name | Ichikawa Shuichi |
| 4th Author's Affiliation | toyohashi university of technology (TUT) |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2016-11-28 15:30:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2016-43 |
| Volume (vol) | vol.116 |
| Number (no) | no.332 |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2016-11-21 (RECONF) |
[Return to Top Page]