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| Presentation | 2016-11-29 09:00 Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB) Yusuke Yoshida, Kimiyoshi Usami (Shibaura Institute of Tech.)  VLD2016-53 DC2016-47 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We focus on the Standard Cell Memory (SCM) as another option to supersede SRAM for low-voltage operation. This paper describes a design of low-power SCM using Silicon-on-Thin-BOX (SOTB). In particular, we present automatic place and routing(P&R) methodology for optimal body-bias separation(BBS) for SCM. Simulation results demonstrated that proposed automatic P&R methodology can reduce wire length by 22% and energy consumption by 57% as compared to the standard digital flow. We also found that the proposed SCM operates at the minimum energy point (0.3V) with 3.7fJ energy per bit-access because we can reduce leakage energy in Near-Vth/Sub-Vth region by optimal BBS. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Silicon-on-Thin-BOX MOSFET / Body Bias / Standard Cell Memory / Ultra-low voltage operation / Low-power / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 330, VLD2016-53, pp. 55-60, Nov. 2016. | |
| Paper # | VLD2016-53 | |
| Date of Issue | 2016-11-21 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2016-53 DC2016-47 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF CPM ICD IE |
| Conference Date | 2016-11-28 - 2016-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB) |
| Sub Title (in English) | |
| Keyword(1) | Silicon-on-Thin-BOX MOSFET |
| Keyword(2) | Body Bias |
| Keyword(3) | Standard Cell Memory |
| Keyword(4) | Ultra-low voltage operation |
| Keyword(5) | Low-power |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yusuke Yoshida |
| 1st Author's Affiliation | Shibaura Institute of Technolog (Shibaura Institute of Tech.) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technolog (Shibaura Institute of Tech.) |
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| Speaker | Author-1 |
| Date Time | 2016-11-29 09:00:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2016-53, DC2016-47 |
| Volume (vol) | vol.116 |
| Number (no) | no.330(VLD), no.331(DC) |
| Page | pp.55-60 |
| #Pages | 6 |
| Date of Issue | 2016-11-21 (VLD, DC) |
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