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| Presentation | 2016-11-29 10:55 Development of power estimation tool for three dimensional FPGA Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2016-46 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the large scale integration (LSI) rather than miniaturization. However, because the through-silicon-via(TSV) of the vertical connection has a large area overhead, we have introduced 3D-FPGA which requires smaller number of TV. In addition, in the new process as a result of improvements and leakage power of the operating speed, and low power consumption design is required. However, it is difficult to perform an architecture exploration of the 3D-FPGA with existing power analysis tool. Therefore, we propose beginning with the a variety of architecture in the corresponding possible power analysis tool for 3D-FPGA in this paper, to evaluate the power estimation of the 3D-FPGA. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | 3D-FPGA / face-down stacking / TSV / power comsumption / switching activity / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 332, RECONF2016-46, pp. 35-40, Nov. 2016. | |
| Paper # | RECONF2016-46 | |
| Date of Issue | 2016-11-21 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2016-46 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF CPM ICD IE |
| Conference Date | 2016-11-28 - 2016-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of power estimation tool for three dimensional FPGA |
| Sub Title (in English) | |
| Keyword(1) | 3D-FPGA |
| Keyword(2) | face-down stacking |
| Keyword(3) | TSV |
| Keyword(4) | power comsumption |
| Keyword(5) | switching activity |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masato Ikebe |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Qian Zhao |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 5th Author's Name | Morihiro Kuga |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 6th Author's Name | Toshinori Sueyoshi |
| 6th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2016-11-29 10:55:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2016-46 |
| Volume (vol) | vol.116 |
| Number (no) | no.332 |
| Page | pp.35-40 |
| #Pages | 6 |
| Date of Issue | 2016-11-21 (RECONF) |
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