Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2016-12-12 15:15
Study of the inverter circuit of DNA/Si-MOSFET due to the parasitic capacitance control
Hibiki Nakano, Matsuo Naoto, Akira Heya, Tadao Takada, Kazusige Yamana (Univ. of Hyogo), Tadashi Sato, Shin Yokoyama (Univ. Hiroshima) EID2016-23 SDM2016-104
Abstract (in Japanese) (See Japanese page) 
(in English) An input/output characteristics of the inverter composed of the DNA/Si-MOSFET and the parasitic capacity was studied. The DNA was bridged between the Si electrodes those serve as the source and drain with the 120nm-gap-length. At VDD = 0 V and VDD = 3V, the output characteristic was almost the same. The remain of this phenomenon is that the space charge layer of the DNA/Si-MOSFET charge due to the charge capture and emission and the parasitic capacitance charge synchronized with the gate voltage.
Keyword (in Japanese) (See Japanese page) 
(in English) DNA/Si-MOSFET / inverter / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 355, SDM2016-104, pp. 63-66, Dec. 2016.
Paper # SDM2016-104 
Date of Issue 2016-12-05 (EID, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF EID2016-23 SDM2016-104

Conference Information
Committee SDM EID  
Conference Date 2016-12-12 - 2016-12-12 
Place (in Japanese) (See Japanese page) 
Place (in English) NAIST 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Fabrication and Evaluation of Silicon Related Materials 
Paper Information
Registration To SDM 
Conference Code 2016-12-SDM-EID 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study of the inverter circuit of DNA/Si-MOSFET due to the parasitic capacitance control 
Sub Title (in English)  
Keyword(1) DNA/Si-MOSFET  
Keyword(2) inverter  
Keyword(3)  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hibiki Nakano  
1st Author's Affiliation University of Hyogo (Univ. of Hyogo)
2nd Author's Name Matsuo Naoto  
2nd Author's Affiliation University of Hyogo (Univ. of Hyogo)
3rd Author's Name Akira Heya  
3rd Author's Affiliation University of Hyogo (Univ. of Hyogo)
4th Author's Name Tadao Takada  
4th Author's Affiliation University of Hyogo (Univ. of Hyogo)
5th Author's Name Kazusige Yamana  
5th Author's Affiliation University of Hyogo (Univ. of Hyogo)
6th Author's Name Tadashi Sato  
6th Author's Affiliation Hiroshima University (Univ. Hiroshima)
7th Author's Name Shin Yokoyama  
7th Author's Affiliation Hiroshima University (Univ. Hiroshima)
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2016-12-12 15:15:00 
Presentation Time 15 minutes 
Registration for SDM 
Paper # EID2016-23, SDM2016-104 
Volume (vol) vol.116 
Number (no) no.354(EID), no.355(SDM) 
Page pp.63-66 
#Pages 4 
Date of Issue 2016-12-05 (EID, SDM) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan