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Paper Abstract and Keywords
Presentation 2017-02-21 14:25
An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States
Morito Niseki, Toshinori Hosokawa (Nihon Univ.), Msayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2016-79
Abstract (in Japanese) (See Japanese page) 
(in English) Scan design has problems such as large hardware overhead and long test application time. Non-scan based test generation is required to resolve the above mentioned problems. However, it is hard to achieve high fault efficiency using non-scan based test generation and an untestable fault identification is especially time-consuming. Therefore, untestable fault identification methods before test generation have been proposed to reduce test generation time. In this paper, an unreachable state identification method, which identifies whether states on a few flip-flops are justified using SAT, is proposed and an untestable fault identification method is proposed using the unreachable states and time expansion models. Untestable faults are identified by applying the combination of conventional methods and our proposed method to ISCAS’89 benchmark circuits, and the number of untestable faults is evaluated.
Keyword (in Japanese) (See Japanese page) 
(in English) sequential circuits / untestable faults / unreachable states / time expansion models / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 466, DC2016-79, pp. 29-34, Feb. 2017.
Paper # DC2016-79 
Date of Issue 2017-02-14 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2017-02-21 - 2017-02-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc 
Paper Information
Registration To DC 
Conference Code 2017-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States 
Sub Title (in English)  
Keyword(1) sequential circuits  
Keyword(2) untestable faults  
Keyword(3) unreachable states  
Keyword(4) time expansion models  
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1st Author's Name Morito Niseki  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Msayoshi Yoshimura  
3rd Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ.)
4th Author's Name Masayuki Arai  
4th Author's Affiliation Nihon University (Nihon Univ.)
5th Author's Name Hiroyuki Yotsuyanagi  
5th Author's Affiliation Tokushima University (Tokushima Univ.)
6th Author's Name Masaki Hashizume  
6th Author's Affiliation Tokushima University (Tokushima Univ.)
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Speaker Author-1 
Date Time 2017-02-21 14:25:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2016-79 
Volume (vol) vol.116 
Number (no) no.466 
Page pp.29-34 
#Pages 6 
Date of Issue 2017-02-14 (DC) 

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