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| Presentation | 2017-03-02 13:55 [Invited Talk] IP Timing Constraints Promotion Challenges -- A method to automatically generate SoC Timing Constraints -- Tatsuya Nakae, Ichiro Shiihara (Socionext)  VLD2016-116 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | It is common that recent SoC is integrated with more than 10 functional IPs which are not only in-house designs but also coming from 3rd-parties. Mostly timing constraints of those IPs are provided in format of SDC, then they are promoted onto whole chip level with that of UDL together. Due to increase of numbers of IPs on SoC, complexity of work to promote those SDCs on whole chip and to verify it is tough and time consuming tasks. Socionext has developed a method to promote SDCs of IPs onto whole chip level with improving productivity of those tasks as collaboration with Excellicon which is EDA company in US. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SoC / IP / SDC / Timing constraint / Promotion / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 478, VLD2016-116, pp. 81-81, March 2017. | |
| Paper # | VLD2016-116 | |
| Date of Issue | 2017-02-22 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2016-116 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2017-03-01 - 2017-03-03 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2017-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | IP Timing Constraints Promotion Challenges |
| Sub Title (in English) | A method to automatically generate SoC Timing Constraints |
| Keyword(1) | SoC |
| Keyword(2) | IP |
| Keyword(3) | SDC |
| Keyword(4) | Timing constraint |
| Keyword(5) | Promotion |
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| Keyword(8) | |
| 1st Author's Name | Tatsuya Nakae |
| 1st Author's Affiliation | Socionext Inc. (Socionext) |
| 2nd Author's Name | Ichiro Shiihara |
| 2nd Author's Affiliation | Socionext Inc. (Socionext) |
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| Speaker | Author-1 |
| Date Time | 2017-03-02 13:55:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2016-116 |
| Volume (vol) | vol.116 |
| Number (no) | no.478 |
| Page | p.81 |
| #Pages | 1 |
| Date of Issue | 2017-02-22 (VLD) |
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