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Paper Abstract and Keywords
Presentation 2017-03-10 13:10
Development and Trial Evaluation of CPU Simulator with Register-transfer level Micro-Operation
Shinya Hara, Yoshiro Imai (Kagawa Univ.) ET2016-113
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a new educational tool for Computer Architecture, which can provide simulation of assembly program code (instead of machine language), demonstration of several kinds of sample programs and visualization of register-transfer-level structure/behavior, namely micro-operation. Our educational tool for CPU simulation has been designed and implemented in Javascript language as Web service. Its users select simulation modes by micro step, by machine cycle and by automatic repetition of such cycles. So they can learn how a computer works graphically, recognize inner structure of CPU and understand micro-operation based behavior of CPU. Our Simulator has been also evaluated through some kinds of questionnaires by users/learners in classroom lectures. It is confirmed that the simulator has been very useful and effective to learn Computer Architecture and behavior/organization of CPU by means of its application.
Keyword (in Japanese) (See Japanese page) 
(in English) Educational Visualization / Computer Simulation at Register-transfer level / e-Learning / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 517, ET2016-113, pp. 111-116, March 2017.
Paper # ET2016-113 
Date of Issue 2017-03-03 (ET) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ET2016-113

Conference Information
Committee ET  
Conference Date 2017-03-10 - 2017-03-10 
Place (in Japanese) (See Japanese page) 
Place (in English) National Institute of Technology, Niihama College 
Topics (in Japanese) (See Japanese page) 
Topics (in English) STEM (Science, Technology, Engineering and Mathematics) Education, etc. 
Paper Information
Registration To ET 
Conference Code 2017-03-ET 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development and Trial Evaluation of CPU Simulator with Register-transfer level Micro-Operation 
Sub Title (in English)  
Keyword(1) Educational Visualization  
Keyword(2) Computer Simulation at Register-transfer level  
Keyword(3) e-Learning  
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1st Author's Name Shinya Hara  
1st Author's Affiliation Kagawa University (Kagawa Univ.)
2nd Author's Name Yoshiro Imai  
2nd Author's Affiliation Kagawa University (Kagawa Univ.)
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Speaker Author-1 
Date Time 2017-03-10 13:10:00 
Presentation Time 25 minutes 
Registration for ET 
Paper # ET2016-113 
Volume (vol) vol.116 
Number (no) no.517 
Page pp.111-116 
#Pages
Date of Issue 2017-03-03 (ET) 


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