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Paper Abstract and Keywords
Presentation 2017-03-10 14:50
Double-precision floating-point logarithm calculation method for FPGA
Yasufumi Fujiwara, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) CPSY2016-156 DC2016-102
Abstract (in Japanese) (See Japanese page) 
(in English) Floating-point arithmetic standard IEEE 754 was revised in 2008, and it presents 36 functions that should be calculated correctly. And, due to the high performance of the FPGA, there is a movement to use the FPGA as an accelerator of a data center or supercomputer. At this time, we can expect improvement in performance by configuring circuits for function calculation on the FPGA. For that purpose we are planning a double precision floating point function calculation FPGA library. In this research, we propose a calculation method for FPGA which computes double precision logarithmic function conforming to IEEE 754-2008 standard. In the method, we perform multilevel argument reduction using tables and multiplications, and approximation using Taylor expansion. In addition, by correcting the value when the rounding is mistaked, intermediate precision necessary for accurate rounding is reduced. There is a tradeoff between the number of argument reductions and the order of approximation, and we describe the method of determining these parameters.
Keyword (in Japanese) (See Japanese page) 
(in English) IEEE754-2008 / double-precision / log function / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 510, CPSY2016-156, pp. 363-367, March 2017.
Paper # CPSY2016-156 
Date of Issue 2017-03-02 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Conference Date 2017-03-09 - 2017-03-10 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumejima Island 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET20167 
Paper Information
Registration To CPSY 
Conference Code 2017-03-CPSY-DC-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Double-precision floating-point logarithm calculation method for FPGA 
Sub Title (in English)  
Keyword(1) IEEE754-2008  
Keyword(2) double-precision  
Keyword(3) log function  
Keyword(4) FPGA  
1st Author's Name Yasufumi Fujiwara  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Kazuyoshi Takagi  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
3rd Author's Name Naofumi Takagi  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker Author-1 
Date Time 2017-03-10 14:50:00 
Presentation Time 20 minutes 
Registration for CPSY 
Paper # CPSY2016-156, DC2016-102 
Volume (vol) vol.116 
Number (no) no.510(CPSY), no.511(DC) 
Page pp.363-367 
Date of Issue 2017-03-02 (CPSY, DC) 

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