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Paper Abstract and Keywords
Presentation 2017-05-22 16:20
CNN implementation on FPGA with Power of 2 Approximation of Weight
Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-6
Abstract (in Japanese) (See Japanese page) 
(in English) Convolutional Neural Network (CNN), a method of Image recognition, is utilized in various fields. Considering CNN implementation to embedded devices, Field Programmable Gate Array (FPGA) is one of the promising medium. The feature of FPGA is high speed processing with low power. There are enormous number of multiply-add operations in Fully Connected (FC) layers of CNN. Therefore, for CNN implementation on FPGA, it is required to consider the resource utilization of multiply-add circuit and memory access for weight of neural network. In this paper, we propose power of 2 approximation of weight in FC layers of CNN. This method enables multiply-add circuit to be configured by Shifter and Adder. Our proposed method improved LUT consumption up to 10.7 times and operating frequency up to 2.6 times. Furthermore, the bit width required for weight was reduced to 3 bits. In this case, deterioration of recognition accuracy was suppressed to about 1%.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Deep Learning / CNN / / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 46, RECONF2017-6, pp. 25-30, May 2017.
Paper # RECONF2017-6 
Date of Issue 2017-05-15 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2017-6

Conference Information
Committee RECONF CPSY DC IPSJ-ARC  
Conference Date 2017-05-22 - 2017-05-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Noboribetsu-Onsen Dai-ichi-Takimoto-Kan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) HotSPA2017: Reconfigurable System, Dependable Computing System, and General Topics 
Paper Information
Registration To RECONF 
Conference Code 2017-05-RECONF-CPSY-DC-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) CNN implementation on FPGA with Power of 2 Approximation of Weight 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Deep Learning  
Keyword(3) CNN  
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1st Author's Name Takahiro Utsunomiya  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Motoki Amagasaki  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Masahiro Iida  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Morihiro Kuga  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2017-05-22 16:20:00 
Presentation Time 20 minutes 
Registration for RECONF 
Paper # RECONF2017-6 
Volume (vol) vol.117 
Number (no) no.46 
Page pp.25-30 
#Pages 6 
Date of Issue 2017-05-15 (RECONF) 

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