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Paper Abstract and Keywords
Presentation 2017-05-25 15:50
Development of Plasmonic Logical Circuit Using Multimode Interference
Ryo Watanabe, Masashi Ota, Yudai Kikuchi, Tomohiro Hirano, Yuya Ishii, Mitsuo Fukuda (TUT) ED2017-20 CPM2017-6 SDM2017-14
Abstract (in Japanese) (See Japanese page) 
(in English) Logic circuits using Surface Plasmon Polaritons(SPPs) as signal carriers have been attracting attentions. Recently, we have demonstrated all-SPP logical operation circuits composed of SiO2 patterns on a Au film. The circuits enable multi-input and multi-output operation using multi-mode interference of SPPs. In this paper, we have reduced the size of the SPP half adder by introducing a mode convertor and confirmed its operation analytically and experimentally. In addition, desired operation of the SPP phase adjustor has been confirmed at different wavelengths ranging from 1260nm to 1360nm.
Keyword (in Japanese) (See Japanese page) 
(in English) Surface Plasmon Polaritons / Multimode Interference / Half Adder / Photonic Device / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 58, ED2017-20, pp. 29-32, May 2017.
Paper # ED2017-20 
Date of Issue 2017-05-18 (ED, CPM, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ED2017-20 CPM2017-6 SDM2017-14

Conference Information
Committee SDM ED CPM  
Conference Date 2017-05-25 - 2017-05-26 
Place (in Japanese) (See Japanese page) 
Place (in English) VBL, Nagoya University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ED 
Conference Code 2017-05-SDM-ED-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of Plasmonic Logical Circuit Using Multimode Interference 
Sub Title (in English)  
Keyword(1) Surface Plasmon Polaritons  
Keyword(2) Multimode Interference  
Keyword(3) Half Adder  
Keyword(4) Photonic Device  
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Keyword(6)  
Keyword(7)  
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1st Author's Name Ryo Watanabe  
1st Author's Affiliation Toyohashi University of Technology (TUT)
2nd Author's Name Masashi Ota  
2nd Author's Affiliation Toyohashi University of Technology (TUT)
3rd Author's Name Yudai Kikuchi  
3rd Author's Affiliation Toyohashi University of Technology (TUT)
4th Author's Name Tomohiro Hirano  
4th Author's Affiliation Toyohashi University of Technology (TUT)
5th Author's Name Yuya Ishii  
5th Author's Affiliation Toyohashi University of Technology (TUT)
6th Author's Name Mitsuo Fukuda  
6th Author's Affiliation Toyohashi University of Technology (TUT)
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Speaker Author-1 
Date Time 2017-05-25 15:50:00 
Presentation Time 25 minutes 
Registration for ED 
Paper # ED2017-20, CPM2017-6, SDM2017-14 
Volume (vol) vol.117 
Number (no) no.58(ED), no.59(CPM), no.60(SDM) 
Page pp.29-32 
#Pages 4 
Date of Issue 2017-05-18 (ED, CPM, SDM) 

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