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Paper Abstract and Keywords
Presentation 2017-06-19 10:40
Placement Algorithm for Mixed-Grained Reconfigurable Architecture with Dedicated Carry Chain
Koki Honda, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) CAS2017-4 VLD2017-7 SIP2017-28 MSS2017-4
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a placement algorithm using analytical placement (AP) and low-temperature simulated annealing (SA) for mixed-grained reconfigurable architecture (MGRA) with dedicated carry chains. The target MGRAs are assumed to have fine-grained blocks with dedicated carry chains to implement high-speed adders/subtracters and coarse-grained blocks to implement complicated arithmetic operations. Although this architecture is expected to enhance the performance of the implemented circuit, placement using simple pair-swap-based SA often converges to a local optimum. The proposed algorithm uses AP to determine an initial placement for SA. The AP explores an appropriate placement of coarse-grained blocks and adders/subtracters consisting of fine-grained blocks and dedicated carry chains. On the other hand, SA is mainly used to determine optimal placement of the remaining fine-grained blocks. The evaluations show that the proposed algorithm reduces the placement cost, critical path delay, and runtime by 18.4%, 6.0%, and 67.6% on average, respectively, over the Versatile Place and Route (VPR). The benchmark includes circuits consisting of only fine-grained logic. Hence, the proposed algorithm is expected to improve the placement quality for a wide range of application circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) analytical placement / low-temperature simulated annealing / initial placement / initial temperature / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 97, VLD2017-7, pp. 19-24, June 2017.
Paper # VLD2017-7 
Date of Issue 2017-06-12 (CAS, VLD, SIP, MSS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2017-4 VLD2017-7 SIP2017-28 MSS2017-4

Conference Information
Committee SIP CAS MSS VLD  
Conference Date 2017-06-19 - 2017-06-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Niigata University, Ikarashi Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2017-06-SIP-CAS-MSS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Placement Algorithm for Mixed-Grained Reconfigurable Architecture with Dedicated Carry Chain 
Sub Title (in English)  
Keyword(1) analytical placement  
Keyword(2) low-temperature simulated annealing  
Keyword(3) initial placement  
Keyword(4) initial temperature  
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1st Author's Name Koki Honda  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Takashi Imagawa  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name Hiroyuki Ochi  
3rd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
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Speaker Author-1 
Date Time 2017-06-19 10:40:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # CAS2017-4, VLD2017-7, SIP2017-28, MSS2017-4 
Volume (vol) vol.117 
Number (no) no.96(CAS), no.97(VLD), no.98(SIP), no.99(MSS) 
Page pp.19-24 
#Pages 6 
Date of Issue 2017-06-12 (CAS, VLD, SIP, MSS) 

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