Paper Abstract and Keywords |
Presentation |
2017-07-27 14:00
Reducing Number of Slots in Circuit-switched Network for Parallel Computers Yao Hu (NII), Tomohiro Kudoh (Univ. of Tokyo), Michihiro Koibuchi (NII) CPSY2017-26 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Network congestion usually happens in supercomputers and datacenter networks. This would lead to increased communication time. In this report, we propose a TDM-based circuit switching network to avoid the network congestion. Each switch in the network caches (reads) incoming data in an input slot (buffer) and later transfers (writes) it to an output slot (buffer). The connection between the input slot and the output slot is established beforehand. The read and write operations on input and output slots are not synchronized but with the same frequency. Thus the whole network guarantees the lowest bandwidth and the largest latency for each communication node pair. The number of total slots for every switch is a direct factor to affect the end-to-end latency. To reduce the required number of slots in the network, we propose a method to automatically generate an interconnection topology according to a given communication pattern and maximum switch degree. Evaluation results show that the number of network resources can be reduced by the proposed topology generator when compared to a 2-D mesh or torus. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
datacenter network / circuit switching / interconnection network / time division multiplexing (TDM) / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 153, CPSY2017-26, pp. 111-116, July 2017. |
Paper # |
CPSY2017-26 |
Date of Issue |
2017-07-19 (CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2017-26 |
Conference Information |
Committee |
CPSY DC IPSJ-ARC |
Conference Date |
2017-07-26 - 2017-07-28 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Akita Atorion-Building (Akita) |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Parallel, Distributed and Cooperative Processing |
Paper Information |
Registration To |
CPSY |
Conference Code |
2017-07-CPSY-DC-ARC |
Language |
English (Japanese title is available) |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Reducing Number of Slots in Circuit-switched Network for Parallel Computers |
Sub Title (in English) |
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Keyword(1) |
datacenter network |
Keyword(2) |
circuit switching |
Keyword(3) |
interconnection network |
Keyword(4) |
time division multiplexing (TDM) |
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1st Author's Name |
Yao Hu |
1st Author's Affiliation |
National Institute of Informatics (NII) |
2nd Author's Name |
Tomohiro Kudoh |
2nd Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
3rd Author's Name |
Michihiro Koibuchi |
3rd Author's Affiliation |
National Institute of Informatics (NII) |
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Speaker |
Author-1 |
Date Time |
2017-07-27 14:00:00 |
Presentation Time |
30 minutes |
Registration for |
CPSY |
Paper # |
CPSY2017-26 |
Volume (vol) |
vol.117 |
Number (no) |
no.153 |
Page |
pp.111-116 |
#Pages |
6 |
Date of Issue |
2017-07-19 (CPSY) |