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Paper Abstract and Keywords
Presentation 2017-07-31 12:00
TCAD Simulation of C-TFET Circuit with Drain Offset Structure
Hidehiro Asai, Takahiro Mori, Junich Hattori, Koichi Fukuda, Kazuhiko Endo, Takashi Matsukawa (AIST) SDM2017-35 ICD2017-23
Abstract (in Japanese) (See Japanese page) 
(in English) We have performed TCAD simulation for a ring oscillator composed of complementary Tunnel Field Effect Transistors (C-TFETs), and analyzed the effect of drain-offset structure on the circuit characteristics. The drain-offset structure lowers the OFF current from the drain edge, and this unable us to shrink the gate length of the TFETs. Furthermore, the reduction of gate-drain capacitance (CGD) enhances the oscillation frequency of the ring oscillator. The enhancement effect of frequency by the drain-offset structure is strongly related to the unique dependence of CGD on the drain voltage, and affected by the operation voltage of the ring oscillator.
Keyword (in Japanese) (See Japanese page) 
(in English) Tunnel FET / Ring oscillator / Drain offset / / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 166, SDM2017-35, pp. 21-24, July 2017.
Paper # SDM2017-35 
Date of Issue 2017-07-24 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2017-35 ICD2017-23

Conference Information
Committee SDM ICD ITE-IST  
Conference Date 2017-07-31 - 2017-08-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido-Univ. Multimedia Education Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low voltage/low power techniques, novel devices, circuits, and applications 
Paper Information
Registration To SDM 
Conference Code 2017-07-SDM-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) TCAD Simulation of C-TFET Circuit with Drain Offset Structure 
Sub Title (in English)  
Keyword(1) Tunnel FET  
Keyword(2) Ring oscillator  
Keyword(3) Drain offset  
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1st Author's Name Hidehiro Asai  
1st Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
2nd Author's Name Takahiro Mori  
2nd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
3rd Author's Name Junich Hattori  
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
4th Author's Name Koichi Fukuda  
4th Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
5th Author's Name Kazuhiko Endo  
5th Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
6th Author's Name Takashi Matsukawa  
6th Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
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Speaker Author-1 
Date Time 2017-07-31 12:00:00 
Presentation Time 25 minutes 
Registration for SDM 
Paper # SDM2017-35, ICD2017-23 
Volume (vol) vol.117 
Number (no) no.166(SDM), no.167(ICD) 
Page pp.21-24 
#Pages 4 
Date of Issue 2017-07-24 (SDM, ICD) 

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