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Paper Abstract and Keywords
Presentation 2017-09-08 14:00
Joint State Estimation and Decoding of Low-Density Parity-Check Codes for Racetrack Memories
Ryo Shibata, Gou Hosoya, Hiroyuki Yashima (TUS) IT2017-45
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, a non-volatile memory with high density and low delay, called Racetrack Memory (RM), has attracted much attention.
In RM, data is disturbed by shift operations resulting position errors, i.e. insertion/deletion errors.
For a high speed reading in RM,
reading of data with multiple read heads has been investigated.
In this paper,
we define a channel model of insertion/deletion errors with multiple read heads.
Moreover, we propose a decoding algorithm of low-density parity-check (LDPC) codes for such channel.
We show by simulations that bit error rate (BER) comparison in terms of different numbers of read heads and data size,
and we show effectiveness of the proposed decoding algorithm.
Keyword (in Japanese) (See Japanese page) 
(in English) LDPC codes / insertion/deletion error / synchronization error / racetrack memory / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 208, IT2017-45, pp. 37-42, Sept. 2017.
Paper # IT2017-45 
Date of Issue 2017-09-01 (IT) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF IT2017-45

Conference Information
Committee IT  
Conference Date 2017-09-08 - 2017-09-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Centcore Yamaguchi Hotel 
Topics (in Japanese) (See Japanese page) 
Topics (in English) error correcting codes, general 
Paper Information
Registration To IT 
Conference Code 2017-09-IT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Joint State Estimation and Decoding of Low-Density Parity-Check Codes for Racetrack Memories 
Sub Title (in English)  
Keyword(1) LDPC codes  
Keyword(2) insertion/deletion error  
Keyword(3) synchronization error  
Keyword(4) racetrack memory  
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Keyword(6)  
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1st Author's Name Ryo Shibata  
1st Author's Affiliation Tokyo University of Science (TUS)
2nd Author's Name Gou Hosoya  
2nd Author's Affiliation Tokyo University of Science (TUS)
3rd Author's Name Hiroyuki Yashima  
3rd Author's Affiliation Tokyo University of Science (TUS)
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Speaker Author-1 
Date Time 2017-09-08 14:00:00 
Presentation Time 25 minutes 
Registration for IT 
Paper # IT2017-45 
Volume (vol) vol.117 
Number (no) no.208 
Page pp.37-42 
#Pages
Date of Issue 2017-09-01 (IT) 


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