Paper Abstract and Keywords |
Presentation |
2017-09-25 13:55
A Study of Applicability of FPGA Dynamic Partial Reconfiguration Technique on COTS-based Carrier Network Equipment with HW/SW Co-design Scheme Toru Homemoto, Hisaharu Ishii, Toshiya Matsuda, Masaru Katayama, Kazuyuki Matsumura (NTT) RECONF2017-25 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The authors consider applying FPGA Dynamic Partial Reconfiguration (DPR) technique to carrier network equipment built with FPGA accelerator board and OpenCL C based programming, to achieve reduction of compiling time of circuit configuration and In Service Software Upgrade (ISSU) without using duplicated data plane. In this paper, assembling DPR areas into a straight chain and applying one-liner programming scheme are introduced and evaluated through a partial implementation of them. The result shows the DPR areas with GNU coreutils base64 command are expected to be placed 21 stages without ISSU and 12 stages with ISSU on Intel Stratix V SGXEA7N FPGA with 50% utilization. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Network Processing / FPGA Dynamic Partial Reconfiguration / In Service Software Upgrade / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 221, RECONF2017-25, pp. 19-24, Sept. 2017. |
Paper # |
RECONF2017-25 |
Date of Issue |
2017-09-18 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
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RECONF2017-25 |
Conference Information |
Committee |
RECONF |
Conference Date |
2017-09-25 - 2017-09-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
DWANGO Co., Ltd. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2017-09-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Study of Applicability of FPGA Dynamic Partial Reconfiguration Technique on COTS-based Carrier Network Equipment with HW/SW Co-design Scheme |
Sub Title (in English) |
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Keyword(1) |
Network Processing |
Keyword(2) |
FPGA Dynamic Partial Reconfiguration |
Keyword(3) |
In Service Software Upgrade |
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1st Author's Name |
Toru Homemoto |
1st Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
2nd Author's Name |
Hisaharu Ishii |
2nd Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
3rd Author's Name |
Toshiya Matsuda |
3rd Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
4th Author's Name |
Masaru Katayama |
4th Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
5th Author's Name |
Kazuyuki Matsumura |
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Nippon Telegraph and Telephone Corporation (NTT) |
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Speaker |
Author-1 |
Date Time |
2017-09-25 13:55:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2017-25 |
Volume (vol) |
vol.117 |
Number (no) |
no.221 |
Page |
pp.19-24 |
#Pages |
6 |
Date of Issue |
2017-09-18 (RECONF) |
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