Paper Abstract and Keywords |
Presentation |
2017-09-26 14:20
Implementing RISC-V with a Python-Based High-Level Synthesis Compiler Ryouzaburo Suzuki, Hiroaki Kataoka (Sinby) RECONF2017-36 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
During the last decade, the environment of field-programmable gate array (FPGA) development has changed rapidly, and the complexity of applications is increasing every year. As a result, design methodologies with higher levels of abstraction are required for both synthesis and verification processes, and high-level synthesis (HLS) compilers have become essential to support such methodologies. We have already shown a design methodology with a high level of abstraction that uses Polyphony, which is a Python-based HLS compiler.
In this paper, we present different scenarios written in a Python-based HLS language for implementing RISC-V. By using workers, queues and ports of a message-passing mechanism, an HLS compiler with no control over clock-level timing can simulate and evaluate a pipelining architecture such as RISC-V. This high-abstraction-level methodology results in expedited development and enhanced readability. Designers can then develop complex systems with FPGAs by building processors in an HLS language that has no inherent expressions to control clock-level timing. What all this suggests is that, with further optimized compilers, building high-performance systems for stream-processing in an HLS language may be achieved in the near future. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / Python / HLS / RISC-V / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 221, RECONF2017-36, pp. 81-86, Sept. 2017. |
Paper # |
RECONF2017-36 |
Date of Issue |
2017-09-18 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
Download PDF |
RECONF2017-36 |
Conference Information |
Committee |
RECONF |
Conference Date |
2017-09-25 - 2017-09-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
DWANGO Co., Ltd. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2017-09-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Implementing RISC-V with a Python-Based High-Level Synthesis Compiler |
Sub Title (in English) |
|
Keyword(1) |
FPGA |
Keyword(2) |
Python |
Keyword(3) |
HLS |
Keyword(4) |
RISC-V |
Keyword(5) |
|
Keyword(6) |
|
Keyword(7) |
|
Keyword(8) |
|
1st Author's Name |
Ryouzaburo Suzuki |
1st Author's Affiliation |
Sinby Corporation (Sinby) |
2nd Author's Name |
Hiroaki Kataoka |
2nd Author's Affiliation |
Sinby Corporation (Sinby) |
3rd Author's Name |
|
3rd Author's Affiliation |
() |
4th Author's Name |
|
4th Author's Affiliation |
() |
5th Author's Name |
|
5th Author's Affiliation |
() |
6th Author's Name |
|
6th Author's Affiliation |
() |
7th Author's Name |
|
7th Author's Affiliation |
() |
8th Author's Name |
|
8th Author's Affiliation |
() |
9th Author's Name |
|
9th Author's Affiliation |
() |
10th Author's Name |
|
10th Author's Affiliation |
() |
11th Author's Name |
|
11th Author's Affiliation |
() |
12th Author's Name |
|
12th Author's Affiliation |
() |
13th Author's Name |
|
13th Author's Affiliation |
() |
14th Author's Name |
|
14th Author's Affiliation |
() |
15th Author's Name |
|
15th Author's Affiliation |
() |
16th Author's Name |
|
16th Author's Affiliation |
() |
17th Author's Name |
|
17th Author's Affiliation |
() |
18th Author's Name |
|
18th Author's Affiliation |
() |
19th Author's Name |
|
19th Author's Affiliation |
() |
20th Author's Name |
|
20th Author's Affiliation |
() |
Speaker |
Author-1 |
Date Time |
2017-09-26 14:20:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2017-36 |
Volume (vol) |
vol.117 |
Number (no) |
no.221 |
Page |
pp.81-86 |
#Pages |
6 |
Date of Issue |
2017-09-18 (RECONF) |
|