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Paper Abstract and Keywords
Presentation 2017-11-06 15:20
A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation
Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) VLD2017-37 DC2017-43
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the increase in test costs for very large scale integrated circuits (VLSI). Especially DFT methods to reduce the number of test patterns at register transfer level (RTL) are required for the adaptability of traditional VLSI design flows and the reduction of time to search DFT locations. In this paper, we propose a DFT method at RTL to enable hardware elements to be concurrently tested with as small number of test patterns as possible in scan testing. The proposed method enhances the effectiveness of test compaction by enable efficient concurrent testing for hardware elements based on controller augmentation. Experimental results on high-level benchmark circuits show that our proposed method reduced the number of test patterns by 33.47% with 7.12 % area overhead on average.
Keyword (in Japanese) (See Japanese page) 
(in English) test register assignment / design for testability / controller augmentation / invalid test states / test scheduling / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 274, DC2017-43, pp. 61-66, Nov. 2017.
Paper # DC2017-43 
Date of Issue 2017-10-30 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-37 DC2017-43

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2017-11-06 - 2017-11-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto-Kenminkouryukan Parea 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2017 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation 
Sub Title (in English)  
Keyword(1) test register assignment  
Keyword(2) design for testability  
Keyword(3) controller augmentation  
Keyword(4) invalid test states  
Keyword(5) test scheduling  
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1st Author's Name Shun Takeda  
1st Author's Affiliation Nihon University (Nihon Univ)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon University (Nihon Univ)
3rd Author's Name Hiroshi Yamazaki  
3rd Author's Affiliation Nihon University (Nihon Univ)
4th Author's Name Masayoshi Yoshimura  
4th Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ)
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Speaker Author-1 
Date Time 2017-11-06 15:20:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2017-37, DC2017-43 
Volume (vol) vol.117 
Number (no) no.273(VLD), no.274(DC) 
Page pp.61-66 
#Pages 6 
Date of Issue 2017-10-30 (VLD, DC) 

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