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Paper Abstract and Keywords
Presentation 2017-11-07 09:50
Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking
Keishiro Akashi, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2017-42
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years,Three-dimensional (3D) field-programmable gate arrays(FPGAs) are expected to offer higher logic density as well as improved delay in a method different from process shrinking.However, because through-silicon-vias (TSVs) for conventional 3D FPGA interlayer connections have a large area overhead,there is a trade-off between connectivity and small size.In this paper,we compare 2D-FPGA and the architecture that we proposed and evaluate delay,power and area.According to our results,a 2-layer 3D FPGA is excellent in speed and power, and a 4-layer 3D FPGA is best in terms of area.
Keyword (in Japanese) (See Japanese page) 
(in English) 3D-FPGA / Face-down stacking / Face-up stacking / / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 279, RECONF2017-42, pp. 31-36, Nov. 2017.
Paper # RECONF2017-42 
Date of Issue 2017-10-30 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2017-42

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2017-11-06 - 2017-11-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto-Kenminkouryukan Parea 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2017 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking 
Sub Title (in English)  
Keyword(1) 3D-FPGA  
Keyword(2) Face-down stacking  
Keyword(3) Face-up stacking  
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1st Author's Name Keishiro Akashi  
1st Author's Affiliation Kumamoto University (Kumamoto Univ)
2nd Author's Name Motoki Amagasaki  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ)
3rd Author's Name Qian Zhao  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ)
5th Author's Name Morihiro Kuga  
5th Author's Affiliation Kumamoto University (Kumamoto Univ)
6th Author's Name Toshinori Sueyoshi  
6th Author's Affiliation Kumamoto University (Kumamoto Univ)
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Speaker Author-1 
Date Time 2017-11-07 09:50:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2017-42 
Volume (vol) vol.117 
Number (no) no.279 
Page pp.31-36 
#Pages 6 
Date of Issue 2017-10-30 (RECONF) 

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