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Paper Abstract and Keywords
Presentation 2017-11-07 09:50
On low power oriented test pattern compaction using SAT solver
Yusuke Matsunaga (Kyushu Univ.) VLD2017-43 DC2017-49
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a test pattern compaction method under power
consumption constraint, which uses SAT solver based random sampling.
First, candidate patterns are generated using XOR constraint based SAT
model sampling, which adds randomly generated constraints to the original
problem, then test pattern set is derived by solving minimum set
covering problem.
Experiments show that increasing the number of candidate patterns
directly leads better solution, which means the proposed heuristic
is very effective and robust.
Keyword (in Japanese) (See Japanese page) 
(in English) test pattern generation / signal transition activity / SAT / random sampling / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 273, VLD2017-43, pp. 95-99, Nov. 2017.
Paper # VLD2017-43 
Date of Issue 2017-10-30 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-43 DC2017-49

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2017-11-06 - 2017-11-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto-Kenminkouryukan Parea 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2017 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On low power oriented test pattern compaction using SAT solver 
Sub Title (in English)  
Keyword(1) test pattern generation  
Keyword(2) signal transition activity  
Keyword(3) SAT  
Keyword(4) random sampling  
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1st Author's Name Yusuke Matsunaga  
1st Author's Affiliation Kyushu University (Kyushu Univ.)
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Speaker Author-1 
Date Time 2017-11-07 09:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2017-43, DC2017-49 
Volume (vol) vol.117 
Number (no) no.273(VLD), no.274(DC) 
Page pp.95-99 
#Pages 5 
Date of Issue 2017-10-30 (VLD, DC) 

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