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Paper Abstract and Keywords
Presentation 2017-11-07 10:30
Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits
Naoya Kubota, Maki Fujiha, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) VLD2017-47 DC2017-53
Abstract (in Japanese) (See Japanese page) 
(in English) Stochastic computing (SC), which is an approximate computation with probabilities, has attracted at- tention because it has distinct advantages in hardware cost and fault tolerance. In SC, numbers to be calculated are represented by the probabilities of one occurring in binary sequences and the numbers are transformed from binary (or deterministic) numbers by stochastic number generators (SNGs). In this paper, we propose a new SC scheme in which SNGs of an SC circuit exploit the internal signals of its peripheral logic circuits for generating random numbers. Furthermore, we propose an algorithm for appropriately selecting signal lines so as to reduce both of conversion errors and correlation-induced errors
Keyword (in Japanese) (See Japanese page) 
(in English) stochastic computing / stochastic number / conversion error / correlation-induced error / chi-square-value / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 273, VLD2017-47, pp. 115-120, Nov. 2017.
Paper # VLD2017-47 
Date of Issue 2017-10-30 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-47 DC2017-53

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2017-11-06 - 2017-11-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto-Kenminkouryukan Parea 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2017 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits 
Sub Title (in English)  
Keyword(1) stochastic computing  
Keyword(2) stochastic number  
Keyword(3) conversion error  
Keyword(4) correlation-induced error  
Keyword(5) chi-square-value  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Naoya Kubota  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Maki Fujiha  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Hideyuki Ichihara  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Tsuyoshi Iwagaki  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
5th Author's Name Tomoo Inoue  
5th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2017-11-07 10:30:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2017-47, DC2017-53 
Volume (vol) vol.117 
Number (no) no.273(VLD), no.274(DC) 
Page pp.115-120 
#Pages 6 
Date of Issue 2017-10-30 (VLD, DC) 

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