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Paper Abstract and Keywords
Presentation 2017-11-07 10:30
Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on β-Expansion by Eliminating Look-Up Table
Yuji Shindo, Kenshu Seto, Hao San (TCU) VLD2017-44 DC2017-50
Abstract (in Japanese) (See Japanese page) 
(in English) We propose an area reduction method of digital circuit part in analog-to-digital converter (ADC) based on β-expansion. The digital parts of existing β-expansion based ADCs uses lookup tables (LUTs) to estimate effective β values and to convert non-binary numbers to binary numbers. Unfortunately, increasing the conversion precision of the ADCs increases the area of the LUTs. In this work, in order to eliminate the LUTs, we estimate the effective β values by Newton’s method and directly convert non-binary numbers to binary numbers. When the conversion precision of the ADCs is increased, the proposed method reduces the increase of the digital part area compared to the existing LUT-based method.
Keyword (in Japanese) (See Japanese page) 
(in English) AD Converter / High-Level Synthesis / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 273, VLD2017-44, pp. 101-104, Nov. 2017.
Paper # VLD2017-44 
Date of Issue 2017-10-30 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-44 DC2017-50

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2017-11-06 - 2017-11-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto-Kenminkouryukan Parea 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2017 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on β-Expansion by Eliminating Look-Up Table 
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Keyword(1) AD Converter  
Keyword(2) High-Level Synthesis  
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1st Author's Name Yuji Shindo  
1st Author's Affiliation Tokyo City University (TCU)
2nd Author's Name Kenshu Seto  
2nd Author's Affiliation Tokyo City University (TCU)
3rd Author's Name Hao San  
3rd Author's Affiliation Tokyo City University (TCU)
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Speaker Author-1 
Date Time 2017-11-07 10:30:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2017-44, DC2017-50 
Volume (vol) vol.117 
Number (no) no.273(VLD), no.274(DC) 
Page pp.101-104 
#Pages 4 
Date of Issue 2017-10-30 (VLD, DC) 

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