Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2018-01-19 09:40
Overview of an HLS Framework Surpporting IoT/CPS Development
Daichi Teruya, Hironori Nakajo (TUAT) VLD2017-77 CPSY2017-121 RECONF2017-65
Abstract (in Japanese) (See Japanese page) 
(in English) We expect reduce CPU resource consumptions by offloading
processing stream data, which are incessantly generated such as
sensor data and actuators control, into an FPGA. However,
designing a system in which software and hardware operation in
cooperation is cumbersome to take a long time to develop. In
this paper, we propose a co-design environment aiming at
prototyping tools that can be applied to embedded systems with
high real-time demands. By using reactive programming, which is
a programming paradigm describing operations on stream data, we
have developed the system as a framework which can reduce load in
an optimization phase to synthesize circuits. We also aime to
facilitate circuit synthesis in dynamically typed languages by
applying multistage computation to lambda abstraction passed to
higher order functions such as map.
Keyword (in Japanese) (See Japanese page) 
(in English) SoC FPGA / HLS / Development Supporting / / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 379, RECONF2017-65, pp. 89-94, Jan. 2018.
Paper # RECONF2017-65 
Date of Issue 2018-01-11 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-77 CPSY2017-121 RECONF2017-65

Conference Information
Committee IPSJ-ARC VLD CPSY RECONF IPSJ-SLDM  
Conference Date 2018-01-18 - 2018-01-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Raiosha, Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2018-01-ARC-VLD-CPSY-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Overview of an HLS Framework Surpporting IoT/CPS Development 
Sub Title (in English)  
Keyword(1) SoC FPGA  
Keyword(2) HLS  
Keyword(3) Development Supporting  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Daichi Teruya  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Hironori Nakajo  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2018-01-19 09:40:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2017-77, CPSY2017-121, RECONF2017-65 
Volume (vol) vol.117 
Number (no) no.377(VLD), no.378(CPSY), no.379(RECONF) 
Page pp.89-94 
#Pages 6 
Date of Issue 2018-01-11 (VLD, CPSY, RECONF) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan